Decode structure with parallel rotation

Details Decode structure with parallel rotation Decode structure with parallel rotation

2007-09-11

2007-09-11

Chang, Daniel (Department: 2819)

Electronic digital logic circuitry

Function of and, or, nand, nor, or not

Decoding

C365S230060, C711S220000, C711S211000

Reexamination Certificate

active

11274876

ABSTRACT:
A memory subsystem and a method of operating therefor. The memory subsystem includes a memory array having 2nlocations. The memory subsystem includes an address decoder and rotation logic each coupled to receive bits of a first address having n address bits. The rotation logic is also coupled to receive m rotation bits indicating a number of locations the first address is to be shifted if the first address falls within a specified range of addresses. The rotation logic and the address decoder are configured to operate in parallel with each other. Address selection logic is coupled to receive a first plurality of outputs from the address decoder and a second plurality of outputs from the rotation logic and is further configured to select a second address based on the first and second pluralities of outputs.

REFERENCES:
patent: 4935897 (1990-06-01), Kurihara et al.
patent: 6574722 (2003-06-01), Utsumi

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