Decision feedback equalization input buffer

Pulse or digital communications – Equalizers – Automatic

Reexamination Certificate

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Reexamination Certificate

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07542507

ABSTRACT:
In a decision feedback equalization (DFE) input buffer, timing and voltage errors, such as those caused by inter-symbol interference (ISI), are fully compensated. A variable equalizing coefficient is applied that accommodates, and compensates for, a range of timing errors TE or voltage errors VE that may be generated over a range of operating conditions. In this manner, accurate compensation is achieved, allowing for greater signal reliability and higher inter-circuit transfer rates. A decision feedback equalization (DFE) input buffer includes an equalizer that amplifies a difference in voltage level between an input signal and an oversampled signal in response to a variable equalizing control signal, the equalizer generating an amplified output signal. A sampling unit samples the amplified output signal in response to a sampling clock signal to generate the oversampled signal. A phase detector generates a timing control signal for controlling the timing of the activation of the sampling clock signal in response to a phase of the oversampled signal. An equalizing controller modifies the variable equalizing control signal in response to the timing control signal.

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Sohn, Young-Soo, et al., “1 1.35Bbps Decision Feedback Equalizing Receiver fro the SSTL SDRAM Interface with 2X Over-Sampling Phase Detector for Skew Compensation Between Clock and Data,” ESSCIRC 2002, pp. 787-790.
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