Decimating filter

Details Decimating filter Decimating filter

1992-09-15

1994-08-23

Clawson, Jr., Joseph E.

Static information storage and retrieval

Read/write circuit

With shift register

365 49, 365195, 365221, 36523005, 365240, 36518902, G11C 804

Patent

active

053413350

ABSTRACT:
A decimating memory includes a memory having addressable memory locations. The memory forms a plurality of registers, each of the registers including at least one addressable memory location. The plurality of registers form a forward shifting data section and a reverse shifting data section. A first decoder operates the registers in the forward shifting data section and all but a first of the registers in the reverse shifting data section as FIFO registers via read and write addressing of the addressable memory locations to input and output data samples. The read and write addressing of the addressable memory locations is offset with respect to one another to provide a decimation factor. A paintbrush decoder operates the first register in the reverse shifting data section as a LIFO register for reverse sequencing data samples within blocks of data samples received from the forward shifting data section. Each of the registers in the forward shifting and reverse shifting data sections provide an output. An ALU section operates on the outputs and provides a decimating memory output.

REFERENCES:
patent: 4897818 (1990-01-01), Redwine et al.
patent: 4930108 (1990-05-01), Sugiyama
patent: 4961169 (1990-10-01), Matsumura et al.
patent: 5046051 (1991-09-01), Doornhein et al.
patent: 5097447 (1992-03-01), Ogawa et al.
patent: 5206834 (1993-04-01), Okitaka et al.

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