Debugging simulation of a circuit core using pattern...

Computer-aided design and analysis of circuits and semiconductor – Integrated circuit design processing – Testing or evaluating

Reexamination Certificate

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Reexamination Certificate

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07979833

ABSTRACT:
Debugging a simulation of a circuit core uses a pattern recorder, a pattern player and a pattern checker to record input stimuli provided to a first core, record output generated by the first core due to the input stimuli, provide the recorded input stimuli to a second core, and determine whether output generated by the second core due to the recorded input stimuli matches the recorded output generated by the first core due to the input stimuli.

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Sinanoglu et al., “Partial Core Encryption for Performance-Efficient Test of SOCs”, Proceedings of the 2003 IEEE/ACM International Conference on Computer-aided Design, pp. 91-94.
Waveform Analyzer Manual, for DK version 3.0, Celoxica Limited, 2004, p. 1-40.
Post Synthesis Gate Level Simulation using Verilog XL, Post synthesis Verification, EE 512, npu, p. 1-16.

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