Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-09-29
2003-03-11
Beausoliel, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C711S206000, C712S042000
Reexamination Certificate
active
06532553
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to the field of data processing systems. More particularly, this invention relates to debugging data processing systems.
2. Description of the Prior Art
With the advent of increasingly complex data processing systems, and the requirement for shorter development time, it is becoming increasingly important to provide powerful debugging tools to assist in system development. This is particularly the case in deeply embedded systems in which much of the systems state is normally inaccessible.
One way of dealing with the debugging problem is to provide serial scan chains around portions of the circuits of the system to allow input signals to be scanned in and applied to the circuit and output signals to be captured and scanned out of the circuit. This is the JTAG type of debugging scheme.
A problem with the serial scan chain approach to debugging is that the scan chain cells may need to be placed upon critical signal paths within the system slowing the signal paths and limiting the system performance. It is an object of the invention to address the above problems
SUMMERY OF THE INVENTION
Viewed from one aspect the present invention provides data processing apparatus responsive to a sequence of processor instructions containing main processor instructions and coprocessor instructions, said data processing apparatus comprising:
(i) a main processor for executing main processor instructions appearing within said sequence of processor instructions;
(ii) a coprocessor coupled to said main processor for executing coprocessor instructions appearing within said sequence of processor instructions; and
(iii) an instruction insertion mechanism operative in a debugging mode for supplying different processor instructions to said main processor and said coprocessor such that said main processor executes a main processor data capture instruction whilst said coprocessor executes a coprocessor debug data generation instruction whereby debug data is generated under control of said coprocessor and said debug data is captured by said main processor.
In a system having both a coprocessor and a main processor, these different elements may be controlled to cooperate while in a debug mode to recover system state information that would otherwise be difficult to obtain without a disadvantageously extensive use of scan chains. More particularly, whilst the same instruction stream is normally fed to both the main processor and the coprocessor, the invention provides that different instructions may be fed to the main processor and the coprocessor in the debug mode with the main processor being responsive to its instruction to capture debug data that is generated under control of the coprocessor in response to a coprocessor instruction executed at the same time (having been triggered to do so by execution of the main processor instruction).
The coprocessor instruction is decoded and interpreted by the coprocessor in the debug mode in a manner chosen by the system designer and is so potentially able to recover any particular items of system state that the system designer decides in advance and for which the circuitry is provided. The capture of the data by the main processor allows it to be subsequently recovered from the main processor via the normal output mechanisms of the system under control of normal main processor instructions.
In preferred embodiments the main processor data capture instruction transfers the debug data into a register of a register bank within the main processor. This data capture mechanism is both rapid and flexible.
The instruction insertion mechanism could take many forms. The mechanisms that feed the standard instructions to the main processor and the coprocessor when not in debug mode could be used to supply one of the main processor and the coprocessor with instructions during this debug mode with the other of the main processor and the coprocessor being supplied from an alternative source by mechanisms only operative in the debug mode. Alternatively, both the main processor and the coprocessor could be provided with special purpose mechanisms for supplying them with instructions during the debug mode. In this case, scan chains for scanning in instructions to the main processor and the coprocessor are preferred.
The state data generated in response to the coprocessor debug data generation instruction could be transferred to the main processor via a special purpose data path. However, in preferred embodiments the standard data bus that is employed in normal operation may also be employed in debug operation for this purpose.
In order to recover state data from the main processor in the context of a debug operation, a register store scan chain can be provided to capture data being read from a register of the main processor and serially clock that data out from the apparatus.
The above system can be used to recover many types of otherwise inaccessible state data from the data processing system. As an example, it is possible to use this approach to recover data from various peripheral devices if the system designer arranges for the coprocessor debug data generation instructions to be interpreted in that way. However, the invention is particularly well suited to the recovery of data from cache memories and memory management units. In particular, the invention can allow the TAG contents of the CAM and the data contents of the RAM of a cache memory and an MMU to be read relatively rapidly from the system and without impacting the normally critical signal paths between the cache, MMU and main processor by inserting scan chains to capture data values on these paths. The contents of a cache memory or an MMU are often highly significant elements of debug information required during system development.
In high performance systems, the main processor will typically have an instruction pipeline. In this case, the instruction insertion mechanism can comprise a scan chain for inserting an instruction into the fetch stage of this pipeline. In such embodiments the coprocessor typically has a pipeline follower and the coprocessor instructions can similarly be inserted into the fetch stage of this coprocessor pipeline.
In the context of a cache memory or an MMU, the problem of how a particular item of data is to be selected for recovery as debug data may be addressed by using the normal victim select circuitry that in standard operation controls which item is replaced when a new item needs to be inserted in the relevant one of the cache memory or the MMU. In the debug mode this victim selection circuitry can be set up in advance to operate to select a specific desired entry for recovery as the debug data.
Viewed from another aspect the present invention provides a data processing method controlled by a sequence of processor instructions containing main processor instructions and coprocessor instructions, said data processing method comprising the steps of:
(i) executing with a main processor main processor instructions appearing within said sequence of processor instructions;
(ii) executing with a coprocessor coprocessor instructions appearing within said sequence of processor instructions; and
(iii) in a debugging mode, supplying different processor instructions to said main processor and said coprocessor such that said main processor executes a main processor data capture instruction whilst said coprocessor executes a coprocessor debug data generation instruction whereby debug data is generated under control of said coprocessor and said debug data is captured by said main processor.
REFERENCES:
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5542033 (1996-07-01), Dao-Trong et al.
patent: 5588118 (1996-12-01), Mandava et al.
patent: 6026478 (2000-02-01), Dowling
patent: 6321329 (2001-11-01), Jaggar et al.
patent: 0 343 992 (1989-11-01), None
Bull David Michael
Gwilt David John
Middleton Peter Guy
Rose Andrew Christopher
ARM Limited
Beausoliel Robert
Nixon & Vanderhye P.C.
Ziemer Rita A
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