Debug port disable mechanism

Details Debug port disable mechanism Debug port disable mechanism

2006-10-03

2006-10-03

Moise, Emmanuel L. (Department: 2137)

Electrical computers and digital processing systems: support

Digital data processing system initialization or configuration

Loading initialization program

Reexamination Certificate

active

07117352

ABSTRACT:
A circuit generally comprising a debug port and a processor is disclosed. The processor may be configured to (i) bootstrap to a first memory, (ii) disable said debug port while in a first mode of at least three modes, (iii) authenticate said debug port while in a second mode of said modes and (iv) disable said debug port in response to failing said authentication.

REFERENCES:
patent: 5664159 (1997-09-01), Richter et al.
patent: 5704039 (1997-12-01), Yishay et al.
patent: 5944841 (1999-08-01), Christie
patent: 5978937 (1999-11-01), Miyamori et al.
patent: 6289448 (2001-09-01), Marsland
patent: 2002/0062461 (2002-05-01), Nee et al.

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