Debug mode for a superscalar RISC processor

Details Debug mode for a superscalar RISC processor Debug mode for a superscalar RISC processor

1993-12-15

1996-07-16

Beausoliel, Jr., Robert W.

Boots, shoes, and leggings

395375, 36423223, 3642808, 364DIG1, G06F 1134, G06F 930

Patent

active

055375383

ABSTRACT:
A processor system that is switchable between a normal mode of operation without precise floating point exceptions and a debug mode of operation with precise floating point exceptions. The processor system includes a dispatch for dispatching integer and floating point instructions, an integer unit having a multi-stage integer pipeline for executing the integer instructions, and a floating point unit having a multi-stage floating point pipeline for executing the floating point instructions. The system begins operation in the normal mode, and upon receipt of an instruction to "switch to debug mode," the processor switches to the debug mode of operation with precise exceptions. In the debug mode, once a floating point instruction has been dispatched, all other instructions are prevented from being committed until the system determines whether the floating point instruction generates an exception. Thus, permitting the system to signal precise exceptions when not in the normal mode.

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