Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
1999-05-19
2002-09-03
Beausoleil, Robert (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S031000, C714S723000
Reexamination Certificate
active
06446221
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data processing systems. More particularly, this invention relates to debugging mechanisms for data processing systems.
2. Description of the Prior Art
A problem with debugging mechanisms is that they should not interfere with or limit the performance possible during normal operation. As an example, known debugging mechanisms often involve the addition of multiplexers within the data processing paths to allow configuration of the debugging mechanisms, such as programming breakpoints and watchpoints. These additional circuit elements that are only needed for debug purposes can impose signal propagation delays within critical data paths that limit the maximum performance of the data processing system during normal operation.
SUMMARY OF THE INVENTION
Viewed from one aspect the present invention provides an apparatus for processing data, said apparatus comprising:
a main processor responsive to main processor instructions within a stream of instructions input to said main processor to perform main processor operations;
a coprocessor coupled to said main processor via a coprocessor interface and responsive to coprocessor instructions within said stream of instructions to perform coprocessor operations; wherein
said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor.
The invention recognises that the mechanisms and structures normally used for coprocessors can be used to provide a debugging system that has a reduced impact upon the normal operation of the system. Additionally, the main processor is often already designed in a manner to facilitate operating and communicating with coprocessors in a manner that does not restrict the performance of the main processor. The invention exploits this feature by providing a debugging mechanism in the form of a debug coprocessor. This debug coprocessor can be configured via the coprocessor interface in a manner that has little impact upon the normal performance of the main processor.
A particularly effectively way of configuring the debug coprocessor is via one or more debug coprocessor registers.
The coprocessor instruction sets associated with main processor and coprocessor systems typically include coprocessor instructions that write values to registers within a coprocessor or read values from registers within a coprocessor. In this way, configuration data can be written to a debug coprocessor and diagnostic data recovered from a debug coprocessor.
Highly useful debug mechanisms are those capable of performing breakpoint and watchpoint functions. These breakpoint and watchpoint values need to be programmed and stored. This need can be achieved highly effectively by the use of registers within the debug coprocessor to store the desired breakpoint and watchpoint values.
Control data associated with more sophisticated breakpoint and watchpoint operation, such as mask values, enable bits, and mode selection values, may also be efficiently programmed and stored using registers within the debug coprocessor. Accordingly, comparisons against address attributes such as the size of the transfer, the mode (e.g. priveleged/user), an instruction set indicating bit (the ARM Thumb T-bit), etc, may also be made.
The coprocessor registers may be accessed via coprocessor instructions within the instruction stream passed to the main processor. This enables both software running on the data processing system being debugged and an external scanning mechanism to access the coprocessor registers to configure the debugging operation by issuing identical instructions to the main processor. Thus, software running on the main processor core may feed instructions intended for the debug coprocessor into a main processor pipeline in a normal fashion, whereas a scanning mechanism can scan in instructions intended for the debug coprocessor one at a time through an instruction transfer register. These scanned-in instructions then being executed one at a time at full speed by being issued as instructions into the same main processor pipeline.
Alternatively and/or additionally, at least some debug coprocessor registers may be accessed via a serial scan chain operating under control of a scan chain controller. This allows external programming of the debug mechanism in the form of the debug coprocessor to be achieved by external hardware and software.
The registers accessible via scan chain mechanisms preferably include a register for allowing instructions to be serially scanned into the system and then be executed by either the main processor or the debug coprocessor (or any other coprocessor, such as a floating point unit coprocessor, attached to the coprocessor interface).
In a similar manner it is preferable that the registers accessible via scan chain mechanisms include a register for allowing a data value to be serially scanned into the system or out from the system. Applying and/or recovering data values in this way is highly useful in diagnostic operation.
In order to deal with the potential problems of the main processor or a coprocessor trying to access such a data value register at the same time that it was being accessed by the scan chain, preferred embodiments provide such a data value register in the form of two data value registers, one of these being writable by the main processor or a coprocessor and readable by a scan chain and the other of these being readable by the main processor or a coprocessor and writable by a scan chain. This effectively forms a bidirectional communications channel that avoids potential data conflicts.
Another of the registers within the debug coprocessor provided by preferred embodiments is a debug status control register that can be read from and written to and that stores information such as the entry condition into the debug mode, a debug enable bit and flags controlling main processor vector instruction trap operation.
The debug coprocessor also preferably is able to use and to generate control signals that can be passed to the rest of the system to perform functions such as pipeline drains, pipeline holds and instruction cancellation.
The debug coprocessor will typically operate at the same clock frequency as the main processor and any other coprocessors in the system. This facilitates the interactions between these elements using a standard coprocessor interface such that the debug coprocessor has a reduced impact upon the speed of normal operation of the main processor and any other coprocessors. However, the scan chain mechanisms will typically operate at a different, typically asynchronous, clock speed and so the debug coprocessor needs to include circuits that allow these elements within different clock domains to communicate. These extra mechanisms may be isolated within the debug coprocessor in a manner that avoids interference with the normal operation of the other main circuit elements.
Viewed from another aspect the present invention provides a method of processing data, said method comprising the steps of:
in response to main processor instructions within a stream of instructions input to a main processor performing main processor operations;
in response to coprocessor instructions within said stream of instructions controlling a coprocessor coupled to said main processor via a coprocessor interface and to perform coprocessor operations; wherein
said coprocessor is a debug coprocessor operable to at least partially control generation of diagnostic data for debugging said apparatus for processing data and said coprocessor instructions are debug coprocessor instructions that control operation of said debug coprocessor.
REFERENCES:
patent: 5133057 (1992-07-01), Ishii
patent: 5978937 (1999-11-01), Miyamori
patent: 5983338 (1999-11-01), Moyer
patent: 6002881 (1999-12-01), York
patent: 6134652 (2000-10-01), Warren
patent: 6173
Hohl William Adam
Jaggar David Vivian
ARM Limited
Beausoleil Robert
Bonzo Bryce P.
Nixon & Vanderhye P.C.
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