Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Patent
1998-03-04
2000-11-07
Beausoliel, Jr., Robert W.
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
713400, 717 4, G06F 112, G06F 1134
Patent
active
061451002
ABSTRACT:
A system for debugging a processor includes a logic circuit for communicating commands and data between an input/output port which operates at a first clock frequency, and trace control logic which operates at a second clock frequency that is different from the first clock frequency. In some embodiments, the input/output port is a JTAG (Joint Test Action Group) port operating at a maximum clock frequency of 25 MHz and the trace control logic operates at a clock frequency of 33 Mhz, 66 MHz, 99 MHz, or 133 mhz. A suitable JTAG clock frequency is a minimum of either half the CPU internal clock frequency or 2.25 Mhz for synchronizing the internal signals between different clock frequencies. When the input/output port, which is typically a serial/parallel input/output port, writes data to debug registers, including ITCR, DCSR, soft.sub.-- address, and RX.sub.-- DATA registers, timing strobe signals to the registers are synchronized to a processor clock to reduce the synchronization logic for register bits that are used by the processor and trace control logic. By synchronizing the debug register data write operations to the processor clock timing, the data bits of the registers are used by the processor and the trace logic without further synchronization. Advantageously, the amount of synchronization logic is reduced. Synchronizing the signals that cross the blocks with different clock timing facilitates communication between the processor, the trace control logic, and the serial and parallel input/output ports and reduces the amount of synchronization logic.
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Advanced Micro Devices , Inc.
Beausoliel, Jr. Robert W.
Revak Christopher
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