Debug interface including state machines for timing synchronizat

Details Debug interface including state machines for timing synchronizat Debug interface including state machines for timing synchronizat

1998-03-04

2000-11-28

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 38, 712227, G06F 1100

Patent

active

061548561

ABSTRACT:
A system for debugging a processor includes logic circuits for communicating commands and data between a serial input/output port, a trace logic, and the processor. Some embodiments of the debugging system also include a parallel input/output port so that the logic circuits also communicate commands and data between the parallel input/output port, the trace logic, and the processor. The debug system includes a plurality of state machines that read the commands and data from the serial input/output ports. The commands are decoded by a decode logic. Some of the commands, such as commands for reading data from memory, utilize processor intervention and are transferred to the processor for execution. The state machines operate only on a single command at one time so that an active state machine does not accept additional commands until completion of the command that is currently executed. Once execution of the command is complete, the state machines generate an indication of the completion event or condition, typically by setting a flag in a debug register or by asserting a readable output pin. The completion event or condition is accessed by a debug tool such as a host processor, a monitoring tool, or the like.

REFERENCES:
patent: 3707725 (1972-12-01), Dellheim
patent: 4429368 (1984-01-01), Kurii
patent: 4462077 (1984-07-01), York
patent: 4598364 (1986-07-01), Gum et al.
patent: 5058114 (1991-10-01), Kuboki et al.
patent: 5321828 (1994-06-01), Phillips et al.
patent: 5355369 (1994-10-01), Greenbergerl et al.
patent: 5357626 (1994-10-01), Johnson et al.
patent: 5371689 (1994-12-01), Tatsuma
patent: 5394544 (1995-02-01), Motoyama et al.
patent: 5488688 (1996-01-01), Gonzales et al.
patent: 5491793 (1996-02-01), Somasundaram et al.
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5533192 (1996-07-01), Hawley et al.
patent: 5544311 (1996-08-01), Harenberg et al.
patent: 5584038 (1996-12-01), Papworth et al.
patent: 5590354 (1996-12-01), Klapproth et al.
patent: 5615331 (1997-03-01), Toorians et al.
patent: 5630102 (1997-05-01), Johnson et al.
patent: 5642479 (1997-06-01), Flynn
patent: 5724505 (1998-03-01), Argade et al.
patent: 5751942 (1998-05-01), Christensen et al.
patent: 5752013 (1998-05-01), Christensen et al.
patent: 5764885 (1998-06-01), Sites et al.
patent: 5768152 (1998-06-01), Battaline et al.
patent: 5771240 (1998-06-01), Tobin et al.
patent: 5774684 (1998-06-01), Haines et al.
patent: 5774708 (1998-06-01), Klingler
patent: 5802272 (1998-09-01), Sites et al.
patent: 5812562 (1998-09-01), Baeg
patent: 5828824 (1998-10-01), Swoboda
patent: 5828825 (1998-10-01), Eskandari et al.
patent: 5848264 (1998-12-01), Baird et al.
patent: 5867644 (1999-02-01), Ranson et al.
patent: 5901283 (1999-05-01), Kanzaki
patent: 5978902 (1999-11-01), Mann
patent: 5978937 (1999-11-01), Miyamori et al.
patent: 5996092 (1999-11-01), Augsburg et al.
patent: 6041406 (2000-03-01), Mann
OJennes, Dan, "Debugging With Real-Time Trace", Embedded Systems Programming, Aug. 1997, pp. 50-58.
O'Farrell, Ray, "Choosing a Cross-Debugging Methodology", Embedded Systems Programming, Aug. 1997, pp. 84-89.
Ganssle, Jack G., "Vanishing Visibility, Part 2", Embedded Systems Programming, Aug. 1997, pp. 113-115.
Am29040.TM., "29K Family", Microprocessor User's Manual, Advanced Micro Devices, Inc. 1994, pp. 12-1 through 12-26.
Revill, Geoff, "Advanced On-chip Debug for ColdFire Developers", Embedded Systems Engineering, Apr./May 1997, pp. 52-54.
Larus, James R., "Efficient Program Tracing", 8153 Computer, No. 5, Los Alamitos, CA, May 26, 1993, pp. 1-10.
IBM Technical Disclosure Bulletin, "Tailorable Embedded Event Trace", vol. 34, No. 7B, Dec. 1991, pp. 259-261.
Motorola, "Personal Computer- BDM Connection", MEVB Quick Start Guide, pp. 3-5 and 7-2 (admitted prior to Apr. 8, 1997).
Motorola, "CPU32 Reference Manual", Section 7 Development Support, pp. 7-1 through 1-13 (admitted prior to Apr. 8, 1997).
U.S. Patent application Ser. No. 08/949,897, filed Oct. 14, 1997, entitled "Trace Cache for Microprocessor Based Device" by Daniel Mann (copies not provided).
U.S. Patent application Ser. No. 08/923,597, filed Aug. 25, 1997, entitled "Software Debug Port for a Microprocessor" by Daniel Mann and Carl Wakeland (copies not provided).
IBM Technical Disclosure Bulletin, "Trace Array", vol. 35, No. 2, pp. Jul. 1992, 138-140.
K5 HDT, Jan. 11, 1997, pp. 1-6.
IEEE Transactions on Nuclear Science, "A Real Time Integrated Environment for Motorola 680xx-based VME and FASTBUS Modules", vol. 36, No. 5, Oct. 1989, pp. 1701-1705.

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