Debug device for detecting bus transmission and method thereof

Details Debug device for detecting bus transmission and method thereof Debug device for detecting bus transmission and method thereof

2006-12-08

2009-10-27

Baderman, Scott T (Department: 2114)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

Reexamination Certificate

active

07610513

ABSTRACT:
This invention relates to a debug device and method thereof and is applied to detect transmission on a bus in a computer system having a CPU, a north bridge chip and a south bridge chip. The debug device consists of a processing unit, a comparing unit and a recording unit. The processing unit receives a first address signal and a second address signal from the north bridge chip, and correspondingly transmits an index signal and a test data to the north bridge chip. The comparing unit compares the first and the second address signal to generate a comparing signal. And the recording unit records the first and the second address signal and the comparing signal. The north bridge chip connects to the south bridge chip via a bus, and the debug device also connects to the south bridge chip. Therefore the north bridge chip and the debug device transmit to both through the south chip.

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patent: 2004/0177340 (2004-09-01), Hsu et al.
patent: 2008/0148104 (2008-06-01), Brinkman et al.
patent: 2009/0157945 (2009-06-01), Arimilli et al.

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