Debug controller in a data processor and method therefor

Details Debug controller in a data processor and method therefor Debug controller in a data processor and method therefor

2000-02-22

2003-07-08

Beausoliel, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C714S030000, C712S227000, C717S124000

Reexamination Certificate

active

06591378

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a data processing system, and specifically to a method and apparatus for debug handling in a data processing system.
RELATED ART
It is important to provide a useful and cost effective approach for allowing emulation and debug of a data processing system, particularly when the data processing system is implemented on an integrated circuit with limited pins or terminals to communicate information. Most emulation and debug approaches provide a mechanism to allow observability and controllability of portions of circuitry within the data processing system. For example, it is desirable to sample registers, memory, and on-chip peripherals at a given instruction boundary. Many processors perform scanning using a dedicated hardware interface.
To enter a debug session, an instruction and/or data may be marked. The debug session is then entered when the operation is terminated. The debug session allows the user to debug the programming code running on the system by evaluating the state of the machine at the point where the instruction and/or data is marked. This includes examining registers, memory, peripherals, etc. Upon completion of the debug session, execution continues after the last successfully completed instruction. It is desirable to sample the processor's resources after the unsuccessful completion of an instruction, but prior to overwriting the values stored in these resources, such as often occurs on exception handling.
In a pipelined processor architecture, operations are divided into stages, where multiple instructions are moving through the pipeline, with one instruction per each stage. For example, a pipeline often includes the stages: fetch, decode, execute, and writeback. The program counter and instruction register stay ahead of the instruction that is currently in the execution stage, creating a problem on return from debug mode.
Where an exception occurs, the exception handling may overwrite the processor status and return address. For an imprecise machine, the exception results in a non-recoverable state of the processor. One prior art processor allows non-maskable breakpoints that allow the processor to stop, but incur a penalty that it may not be restartable.
A need therefore exists for a method of determining a last unsuccessful instruction which is reexecuted after debug. Similarly, a need exists for a method of debug handling that retains sufficient uncorrupted information to allow return to normal processing.


REFERENCES:
patent: 4796177 (1989-01-01), Nishimura et al.
patent: 5084814 (1992-01-01), Vaglica et al.
patent: 5226129 (1993-07-01), Ooi et al.
patent: 5526485 (1996-06-01), Brodsky
patent: 5530804 (1996-06-01), Edgington et al.
patent: 5533192 (1996-07-01), Hawley et al.
patent: 5704034 (1997-12-01), Circello
patent: 5956494 (1999-09-01), Girardeau et al.
patent: 5956495 (1999-09-01), Kahle et al.
patent: 5983018 (1999-11-01), Kanzaki
patent: 6145097 (2000-11-01), Moyer et al.
patent: 6205560 (2001-03-01), Hervin et al.

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