Debug circuit and microcomputer incorporating debug circuit

Details Debug circuit and microcomputer incorporating debug circuit Debug circuit and microcomputer incorporating debug circuit

1999-04-20

2002-10-08

Beausoleil, Robert (Department: 2184)

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

C703S028000

Reexamination Certificate

active

06463551

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a debug circuit for debugging programs and a microcomputer incorporating the debug circuit.
2. Description of the Related Art
Conventionally, an in-circuit emulator (hereinafter referred to as ICE) are commonly used for debugging programs stored in a microprocessor during program development.
The function of the ICE is to emulate the function of a microprocessor performing a program debug operation. Address and data buses in the microcomputer are connected to a memory in the ICE. The debugging program is down loaded from a host computer to the memory in the ICE. Then, the ICE controls the operation of the microcomputer for the debugging of the program.
Normally, the address and data buses to be connected to the memory in the ICE are not connected to terminals in the LSI because programs are stored in the memory in the microcomputer having a microcontroller incorporated in the LSI. For this reason, it must be required to enter a dedicated operation mode for ICE connection where the address and data buses are connected to the external terminals of the LSI, and the inherent function of the terminals to be used for the address and data buses are emulated in the ICE.
However, because it must be required to use the total number of terminals in the microcomputer for connecting the ICE to the microcomputer as a target system for debugging, it becomes difficult to connect the ICE to the target system according to the increasing of the operation speed of the microcomputer and the increasing of the number of bits per bus. It becomes difficult to emulate the inherent function of terminals to be used for address and data buses, which connect the ICE to the memory, by using the ICE, because various functional devices in addition to the microcontroller of the microcomputer are incorporated in a system LSI in order to form the function of the system LSI.
Based on the background of the conventional ICE described above, the debug circuit
102
to compensate a part of the function of the conventional ICE is incorporated in the microcomputer. Thereby, it is widely used to perform a program-development method in which the debug circuit is connected to the host computer (not shown) through dedicated terminals only for debugging in the LSI.
FIG. 1
is a diagram showing the entire configuration of a LSI incorporating a conventional debug circuit. In
FIG. 1
, the reference number
100
designates a microcomputer, and
102
denotes a debug circuit incorporated in the microcomputer
100
. The debug circuit
102
is connected to an external debugger (omitted from
FIG. 1
) through both a data terminal (DATA terminal) of a plurality of bit lines, a clock terminal (CK terminal) for synchronizing data transfer with a clock signal, and a OE terminal for controlling input/output operation of the data and clock signal. The data transfer operation is performed between the debug circuit
102
and the external debugger (not shown) through the DATA terminal of a plurality of bit lines.
The reference number
103
designates a functional block group having a functional block A and a functional block B incorporated in the LSI. The functional block A is directly connected to a control bus, an address bus, and a data bus in the microcomputer
100
. Each of the control bus, the address bus, and the data bus has a plurality of bit lines. The functional block B is independently separated in configuration from the microcomputer
100
.
The reference number
104
indicates a bus interface,
105
designates a central processing unit (CPU),
106
denotes a memory,
107
designates a down load circuit,
108
indicates a register control circuit,
109
designates a trace control circuit,
110
denotes a comparator, and
111
indicates a register circuit having a plurality of registers 0 to 3.
The description will be given of the operation of the conventional debug circuit incorporated in the microcomputer
100
on the LSI shown in FIG.
1
.
First, the functions (a) to (d) of the debug circuit
102
incorporated in the microcomputer
100
shown in
FIG. 1
will be explained.
(a) Communication function between the debug circuit
102
and the external debugger (not shown).
A host computer (omitted from
FIG. 1
) performs data input/output operation between the host computer and the debug circuit
102
through the external debugger through the CK terminal, the DATA terminal, and the OE terminal. The data transferred from the host computer are input to the debug circuit
102
and then the register control circuit
108
in the debug circuit
102
decodes the data transferred from the host computer and then transfers decoded data to both the down load circuit
107
, the trace control circuit
107
, the comparator
110
, and the register circuit
111
(registers 0 to 3).
(b) Down load function
When programs (as data) generated by the host computer are transferred to the down load control circuit
107
based on the communication function (a) described above, the down load control circuit
107
down loads the programs into the memory
106
through the control bus, the address bus, and the data bus.
(c) Tracing function
The trace control circuit
109
receives control signals indicating the operation state of the CPU
105
through the control bus, the address bus, and the data bus that connect the bus interface
104
to the CPU
105
. The trace control circuit
109
then outputs the control signals indicating the operational state of the CPU
105
to the external debugger (not shown) through the CK terminal, the DATA terminal, and the OE terminal.
(d) Break function
Execution addresses and data of program designated by the host computer are written into the comparator
110
through the external debugger in advance. For example, the comparator
105
outputs an interrupt request to the CPU
105
when the operational state of the CPU
105
is changed and when data on the address bus become equal to data that have been pre-stored therein. After this, the interrupt processing program that has been down loaded into the memory
106
in advance is executed so that the data transfer is performed between the CPU
105
and the external debugger through the register circuit
111
.
According to the functions (a) to (d) of the debug circuit
102
described above, the program debug operation will be executed based on the following manners (1) to (4):
(1) The host computer generates a program.
(2) The program stored in the microcomputer
100
is down loaded into the memory
106
.
(3) Under the instruction generated by and transferred from the host computer, the operational state of the CPU
105
is observed based on the tracing function (c) by the debug circuit
102
that outputs the results of the tracing operation (c).
(4) The break interrupt is generated at the program address indicated by the host computer. Then, in order to obtain the operational state of the CPU
105
, the data communication is performed between the host computer and the debug circuit
102
during the interrupt operation.
Although it is possible to obtain the operational state of the CPU
105
because the conventional debug circuit
102
has the configuration and functions described above, it is difficult to observe the operational state of the CPU
105
by using the tracing function (c) of the debug circuit
102
when the operation of the functional block B becomes more complicated along with the increasing of function of the LSI. This causes to decrease the efficiency of the debug operation for programs.
SUMMARY OF THE INVENTION
Accordingly, an object of the present invention is, with due consideration to the drawbacks of the conventional technique, to provide a debug circuit capable of debugging programs efficiently and a microcomputer incorporating the debug circuit.
In accordance with a preferred embodiment of the present invention, a debug circuit receives trace data from a CPU incorporated in a LSI in synchronization with a standard clock signal used in the CPU when the CPU generates a tr

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