Debug apparatus

Details Debug apparatus Debug apparatus

1998-05-26

2000-12-05

Beausoliel, Jr., Robert W.

Error detection/correction and fault detection/recovery

Data processing system error or fault handling

Reliability and availability

714 34, 714 38, 714 32, 714 47, 714 48, G06F 1300, G06F 1130

Patent

active

061580236

ABSTRACT:
The present invention provides a debug apparatus that can set complex break conditions, minimize a time lag from the detection of a break event to the break an execution of a program, and has a debug function with a necessary minimized break determinator included in a chip. A part of the break conditions in a sequence is set in an external break determinator. The remaining condition other than the part of the conditions is set in an internal break determinator. While monitoring an operation status of a processor executing a program, when the conditions set in the external break determinator are satisfied, a break enable signal is input to an AND logic circuit via a break enable input terminal and is held. When the break determinator detects the satisfaction of the remaining condition stored in the internal break determinator, a break signal is supplied from the AND logic circuit to the CPU, thereby breaking the program without delay.

REFERENCES:
patent: 5740413 (1998-04-01), Alpert et al.
patent: 6065078 (2000-05-01), Falik et al.

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