Electronic digital logic circuitry – Signal sensitivity or transmission integrity – Output switching noise reduction
Reexamination Certificate
2006-06-19
2008-07-15
Chang, Daniel D (Department: 2819)
Electronic digital logic circuitry
Signal sensitivity or transmission integrity
Output switching noise reduction
C326S082000, C327S261000, C323S282000
Reexamination Certificate
active
07400163
ABSTRACT:
In a dead time control circuit, a delay circuit is connected to an input terminal and adapted to delay signals therethrough by a delay time corresponding to a dead time. A logic circuit has a first input connected via the delay circuit to the input terminal, a second input connected directly to the input terminal, and an output connected to an output terminal. The dead time having adjustable temperature characteristics.
REFERENCES:
patent: 2006/0164867 (2006-07-01), Dikken et al.
patent: 6-216750 (1994-08-01), None
patent: 2006352741 (2006-12-01), None
Yanagigawa Hiroshi
Yoshida Mitsuru
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