DDR memory controller

Details DDR memory controller DDR memory controller

2011-07-05

2011-07-05

Stoynov, Stefan (Department: 2116)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

Inhibiting timing generator or component

C713S401000, C713S503000, C326S038000, C326S093000, C365S193000, C365S194000, C365S233130, C702S106000, C702S117000, C702S124000, C711S103000, C711S167000, C711S170000, C714S718000, C714S724000

Reexamination Certificate

active

07975164

ABSTRACT:
A DDR memory controller is described wherein a core domain capture clock is created by programmably delaying the core clock of the memory controller. The delay of this capture clock is calibrated during a power on the initialization sequence in concert with a DDR memory in a system environment, thereby minimizing the effects of system delays and increasing both device and system yield. An additional embodiment also includes programmably delaying the incoming dqs signal.

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Application Note—High Performance DDR3 SDRAM Interface in Virtex-5 Devices Xilinx Corporation—Sep. 24, 2007—p. 10—copy attached.
Application Note—Utilizing Leveling Techniques in DDR3 SDRAM Memory Interfaces Altera Corp—Nov. 2007—p. 2—copy attached.
White Paper—The Love/Hate Relationship with DDR SDRAM Controllers Mosaid Technologies Inc.—Oct. 2006—pp. 7-8—copy attached.

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