DDR II write data capture calibration

Details DDR II write data capture calibration DDR II write data capture calibration

2007-01-16

2007-01-16

Cao, Chun (Department: 2115)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C711S167000, C713S600000

Reexamination Certificate

active

10751437

ABSTRACT:
A calibration circuit for calibrating the input data path of a digital circuit is disclosed. A simple string of a repeating data pattern such as, e.g., “1100,” is sent on the data path. The digital circuit captures the data using a clock signal, examines the data signal for the predetermined pattern and adjusts a delay applied to the data signal until the predetermined pattern is recognized. Then the delay is further adjusted until the predetermined pattern is no longer recognized indicating that an edge of the eye of the data is near a clocking edge of the clocking signal. The delay applied to the data signal is then further adjusted by a predetermined amount to position the clock edge near the center of the data eye.

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