DDR DRAM data coherence scheme

Details DDR DRAM data coherence scheme DDR DRAM data coherence scheme

1999-12-02

2002-09-17

Bragdon, Reginald G. (Department: 2186)

Electrical computers and digital processing systems: memory

Storage accessing and control

Specific memory composition

C711S167000, C365S233100, C365S233500, C365S193000, C365S230040

Reexamination Certificate

active

06453381

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
This invention applies to semimemories and in particular to data coherence for double data rate DRAM.
2. Description of Related Art
In double data rate DRAM's (DDR DRAM's) data is read from and written into the DDR DRAM on both edges of a clock. To maintain data coherence it is necessary to insure a write to and a read from a given cell are actually performed on the same storage cell. Burst read operations in a DDR DRAM requires a starting address and a burst length after which data is presented at a out put after a NOT CAS (column address strobe) latency. To insure read coherence it is necessary to know if the NOT CAS latency is an integer or a non integer to a understand if the first piece of data is to be read with a positive edge or a negative edge of the clock. When writing data there is no NOT CAS latency and the starting address being odd or even is important to maintaining locating the memory cell for storing the data.
In U.S. Pat. No. 5,901,109 (Miura) describes synchronous dynamic random access memory (SDRAM) circuity which provides controls for read and write operations that can be carried out asynchronously al d not constrained by the clock. U.S. Pat. No. 5,892,730 (Sato et al.) describes an SDRAM which cm operate in a pipelined mode or a prefetch mode and allowing multiple data write modes to be implemented in one chip. In U.S. Pat. No. 5,402,388 (Wojcicki et al.) a method is described for adjusting the latency of a SDRAM by adjusting the timing of the CAS with respect to the system clock.
SUMMARY OF THE INVENTION
In this invention data coherence is provided for the reading and writing of a DDR DRAM in burst mode using both the positive and negative edge of the system clock. The data burst can be any length with the starting data being written to or read from either an even or odd address. Subsequent data in the burst being written to or read from an odd address if the starting address was even and an even address if the starting address was odd. To read data a CAS latency established by the BIOS at computer power up determines the number of clock cycles to read first data after the read command is set. A bit switch is used to select the BLSA. The CAS latency can be either an integer number of clock cycles or a non integer number of clock cycles requiring both the CAS latency and the starting address to be considered when reading stored data to maintain coherence.
During a read operation when the burst starting address is even and the CAS latency is an integer, or when the burst starting address is odd and the CAS latency is a non integer, data in the even BLSA and the odd BLSA are clocked directly through to an output multiplexer. The positive edge of the clock is used to clock the even address data to the output multiplexer and the negative edge of the clock is used to clock the odd address data to the output of the multiplexer. When the burst starting address is even and the CAS latency is a non integer, or when the burst starting address is odd and the CAS latency is an integer, data in the even BLSA is connected to the output multiplexer by means of circuitry clocked with the negative edge of the clock, and data in the odd BLSA s connected to the output multiplexer by means of circuitry clocked with the positive edge of the clock.
In a write operation CAS latency is not a factor and the only criteria is connecting the burst data to the proper address locations. For a write operation, burst data bits are strobed by the data strobe (DQS into registers. A positive DQS strobes data into register reg_dqs_p, and a negative DQS strobes data into registers reg_dqs_n. If the burst starting address is even, data strobed into reg_dqs_p is connected to an even BLSA (BLSA_E), and data strobed into reg_dqs_n is connected to an odd BLSA (BLSA_O). If the data burst starting address is odd, data strobed into reg_dqs_p is connected to BLSA_O and data strobed into reg_dqs_n is connected to BLSA_E.
Data coherence is assured by a write followed by a subsequent read of the same data to and from the sam, memory cell. Coherence exist when the burst starting address is even and the first bit at said output is from an even storage address. Both sequential and interleaved data bursts can be read and written with coherence using the methods in this invention.


REFERENCES:
patent: 5402388 (1995-03-01), Wojcicki et al.
patent: 5892730 (1999-04-01), Sato et al.
patent: 5901109 (1999-05-01), Miura
patent: 6078546 (2000-06-01), Lee
patent: 6130853 (2000-10-01), Wang et al.
patent: 6147926 (2000-11-01), Park
patent: 6151271 (2000-11-01), Lee

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