Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2001-08-17
2004-08-17
Moazzami, Nasser (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C711S167000, C365S189020, C365S230040, C365S233100
Reexamination Certificate
active
06779075
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates a memory converter and the apparatus for applying the same. More particularly, the invention relates to a DDR and QDR converter, and an interface, a motherboard, a memory module and a portable computer motherboard using the DDR and QDR converter.
2. Description of the Related Art
Along with the advancement in techniques for wafer fabrication and package process, and in addition to the rapid growth in processing speed of the central processing unit (CPU), various alterations of a computer's memory management have occurred. Demand for access speed has pushed the development of memory from the early dynamic random access memory (RAM), the extended data output random access memory (EDO RAM), to the current synchronous data rate RAM (SDR RAM) and double data rate RAM (DDR RAM). The enhancement of access speed of the memory has caused a higher fabrication cost for various kinds of RAM's.
SUMMARY OF THE INVENTION
The present invention provides a method and a structure with a higher access speed compared to the current memory to significantly improve the efficiency of the DDR RAM's without incurring high fabrication cost. The structure is called “quadruple data rate RAM (QDR)”. The invention includes the formation of the ADR signal system and the conversion method between the DDR and QDR signal systems. The conversion structure and method provided by the invention can be applied to all the electronic equipment that requires RAM, such as interface cards, motherboards and portable computer motherboards.
The DDR and QDR converter provided by the invention has a QDR interface, a DDR interface, a clock controller, a command controller, a state register and a data converter. The QDR interface is used to exchange a signal with a QDR device. The DDR interface is used to exchange a signal with a DDR device. The clock controller converts the clock signal sent from the QDR device into a clock used by the converter and the DDR device. After receiving a QDR command signal from the QDR device, the command controller processes the QDR command signal into a corresponding DDR command signal and outputs the DDR command signal into the DDR device. The state register is used to store data of the mode register set (MRS) and the extended mode register set (EMRS), and to provide conversion data to the command controller for appropriate command and data conversion. The data converter is used to convert the QDR data format into a DDR data format, and convert the DDR data format into a QDR data format.
In one embodiment of the invention, the data converter comprises a data mask and probe controller, a QDR-to-DDR data converter and a DDR-to-QDR data converter. The data mask and probe controller is used to obtain the QM signal and DQS signal of the QDR device. The QM signal is then converted into a DDR QM signal output to the DDR device, while the DQS signal is converted into a data extract signal for the QDR device to extract data from the DDR device. The QDR-to-DDR data converter converts the serial signal of the QDR device into a parallel signal. According to the command of the command controller, the parallel signal is sent to two DDR devices. The DDR-to-QDR data converter converts two data signals of the DDR device into the serial signals used by the QDR device, which are then sent to the QDR device according to the command output from the command controller.
According to the above, a conversion channel is established between QDR and DDR, so that DDR can operate normally in a system or apparatus supporting QDR without converting the system or apparatus into a DDR supporting system or apparatus. The DDR and QDR can thus operate normally simultaneously.
Therefore, the user does not have to buy an additional QDR memory module. The invention uses the existent DDR memory module to upgrade to a memory module with both the DDR and QDR functions.
For the manufacturer, DDR chips with a lower cost can be selected while manufacturing the interface, motherboard and related printed circuit boards to obtain a product with the QDR data process effect. The quality and performance of the product are enhanced without raising the fabrication cost.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 6061292 (2000-05-01), Su et al.
patent: 6275441 (2001-08-01), Oh
patent: 6600693 (2003-07-01), Kim
Chuang Hai Feng
Wu Kun Ho
J.C. Patents
Leadtek Research Inc.
Moazzami Nasser
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