Active solid-state devices (e.g. – transistors – solid-state diode – Integrated circuit structure with electrically isolated... – Passive components in ics
Reexamination Certificate
2003-04-15
2004-11-23
Nelms, David (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Integrated circuit structure with electrically isolated...
Passive components in ics
C257S529000, C257S531000, C257S532000, C438S729000, C438S730000, C438S731000, C216S067000, C216S071000, C156S345420
Reexamination Certificate
active
06822311
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method and device for controlling the diffusion of dopants in a semiconductor substrate.
BACKGROUND OF THE INVENTION
As semiconductor device structure sizes shrink, greater and greater control must be excised to control the formation of the ever shrinking structures. The location and dimensions of the smaller and smaller structures require careful control to ensure proper placement. At the minute dimensions involved, mall errors in misplacement and/or size of structures formed can Tesult in non-functional or mis-functioning devices. Processes involved in semiconductor device manufacture require ever increasing levels of precision to create the desire structures.
Rapid thermal processing is widely used for diffusing dopants in a semiconductor substrate. At the present time for rapid thermal processing, a radiation source, such as a lamp or a hot plate, is used to rapidly heat a workpiece to the desired temperature. That radiation source is then used to maintain the workpiece at that temperature. The radiation source is then used to rapidly cool the workpiece in a controlled fashion. During each of these steps of the typical process, wafer temperature is sensed (either with a pyrometer sensing the infrared radiation of the workpiece or with a thermocouple) and used to provide feedback control of the temperature. When a workpiece is raised to a temperature of sufficient magnitude, diffusion of species within the workpiece begins. Further, the rate of such diffusion is a strong function of the workpiece temperature. Also, the extent of any diffusion is a factor of both temperature magnitude and time-at-temperature. Therefore, when the workpiece is a semiconductor wafer, and the thermal process is a rapid thermal process used for activation annealing of a dopant species, in order to achieve a uniform activation and diffusion of dopant atoms at all sites on the semiconductor wafer, precise control of the temperature of the wafer is essential.
In the more recent silicon-on-insulator technology, it will be desirable to control the diffusion of dopants to a better than 3° C. 3-sigma temperature control. However, because of the limitation in the state of the art rapid thermal processing equipment, only a 5-6° C. 3-sigma temperature control can be achieved at the present time. A number of factors exist that contribute to the temperature control problem. These include the chamber gas flow the chamber doors and robotics, the wafer centering, and slow rate limitation of the lamp heating.
Concerning chamber gas flow, a thermal gradient across the wafer exists due to process gas distribution. In rapid thermal processing equipment, a process gas is introduced (either reactive or inert). The rapid thermal processor is not a thermal equilibrium system (only the workpiece and its support structures are heated). Therefore, the incoming gas is cold, but the gas heats as it travels across the wafer and exits the chamber. This factor creates a temperature gradient of colder temperature near the gas inlet and warmer temperature near the gas outlet on chamber components. That gradient is transferred to the wafer when the wafer is placed into the chamber. Wafer rotation is used to mitigate this effect. However, in state of the art systems equipped with wafer rotation, while this effect is mitigated, it still leaves a distinct signature in that a wafer-rotational period oscillation in temperature is very evident in the signal of fixed pyrometers. This oscillation cannot be damped out because of a lack of lamp zone control, and therefore results in local hot and cold spots on the wafer edge. These hot and cold spots have been directly linked to chips which do not meet performance criteria
In addition, a thermal gradient across the wafer exists due to chamber door and wafer handling equipment. In a similar fashion as mentioned above, since a door must be placed in a processing chamber, and since robotic handlers must insert the workpiece through that door, a cooling effect on chamber internals occurs at the door. Cold gases from the transfer chamber or room air cool the door region; and the robot handler end piece acts as a heat sink and cools the door region. Accordingly, hot and cold spots are created, which are linked to chips which do not meet performance criteria
In the current state of the art, rapid thermal processors support the wafer with a pocketed ring (full edge contact). Hot and cold spots on the wafer edge are known to be created if wafer centering in that support “edge ring” is not accurate to within 0.010-0.015 inches. The wafer rotation used to correct for thermal non-uniformities creates a metastable condition, where any sufficient perturbation of the wafer will result in the wafer centripetally accelerating until it is as off-center as possible. Thus, hot and cold spots due to wafer positioning are often created. These, too, have been directly linked to chips, which have not met their performance criteria.
With respect to slew rate limitations of lamp heating, because W-halogen lamps are built with some kind of enclosure to contain the gas, that enclosure stores a significant amount of heat. This stored heat dampens any high frequency signal, which might be driven into the lamps. And, as chamber rotation speeds increase with rapid thermal processor design evolution (200mm tools rotate at 90 RPM; 300 mm tools will rotate at 150 to 300 RPM), it becomes increasingly difficult to dampen rotation related temperature oscillations with controlled lamps.
The current state of the art of rapid thermal processing technology suffers from limitation of dopant diffusion and thermal budget matching. Concerning diffusion limitations, many technologies make use of very heavy and shallow dopant implants with follow-on anneal for activation and diffusion to achieve a shallow uniform dopant profile. Because of the extent of the diffusion required, very high temperature batch furnace are necessarily utilized. However, these processes present a problem—particularly as wafer size increases because at high temperature batch furnaces produce wafer slip. Thus, it would be desirable to provide a means of increasing the overall anneal diffusion rate so that a single wafer rapid thermal anneal process becomes practical.
Concerning thermal budget matching, an object of some current manufacturing line practices is to qualify both batch and single wafer hot processes for all steps. For example, it is desired to be able to form spacer nitride films in both a batch furnace CVD processor and a single wafer rapid thermal CVD processor. But, since the batch tool keeps a set of 125 wafers at a temperature of about 750° C. for over an hour, the single wafer processor keeps each wafer at about 750° C. for only two minutes. The end result is that the device characteristics of transistors formed with batch nitride depositions differ from those of transistors formed with single wafer depositions. The reason for the difference is that the diffusion resulting from time-at-temperature is significantly different between the two systems. Therefore, a means of increasing the total diffusion of the single wafer process, while keeping the same thermal profile would be desirable.
SUMMARY OF THE INVENTION
The present invention concerns a method for forming a desired junction profile in a semiconductor device. At least one dopant is introduced into a semiconductor substrate. The at least one dopant is diffused in the semiconductor substrate through annealing the semiconductor substrate and the at least one dopant while exposing the semiconductor substrate to a DC and/or AC electric field.
The present invention also relates to a device for forming a desired junction profile in a semiconductor substrate. The device includes means for annealing a semiconductor substrate in which at least one dopant has been diffused. The annealing means includes at least one heat source. The device also includes means for producing a DC and/or AC electric field and exposing the semiconductor substrate
Ballantine Arne W.
Ellis-Monaghan John J.
Furukawa Toshihura
Gilbert Jeffrey D.
Miller Glenn R.
Berry Renee R.
Nelms David
Wyche Myron K.
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