Electronic digital logic circuitry – Clocking or synchronizing of logic stages or gates
Patent
1998-08-04
2000-05-09
Tokar, Michael
Electronic digital logic circuitry
Clocking or synchronizing of logic stages or gates
326 56, 326 82, H03K 1900
Patent
active
060609087
ABSTRACT:
A databus includes n+1 (n.gtoreq.2) lines which form n true-only lines and lead from n input blocks to n output blocks. One of the true-only lines as well as a monitoring line are associated with one of the input blocks which is located at a start of the databus and has the longest signal delay time. A NAND gate is connected downstream of the input block at the start of the databus and has an output connected to each output block.
REFERENCES:
patent: 5708374 (1998-01-01), Durham et al.
patent: 5856746 (1999-01-01), Petrick
Graetz Thoralf
Haerle Dieter
Heyne Patrick
Greenberg Laurence A.
Lerner Herbert L.
Siemens Aktiengesellschaft
Stemer Werner H.
Tokar Michael
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