Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-04-28
2003-01-21
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06510541
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a database used for design of an integrated circuit device and a method for designing an integrated circuit device using such a database. More specifically, the present invention relates to design technology for supporting system-on-chip implementation.
Conventionally, semiconductor devices for an electronic apparatus are fabricated in the following manner. LSIs prepared individually for each type such as a memory and a processor are formed on respective semiconductor chips, and such semiconductor chips are packaged on a motherboard such as a printed board.
In recent years, in an attempt of utilizing electronic apparatuses in a wider range of fields, semiconductor devices used for electronic apparatuses have been requested to reduce the size, weight, power consumption, and cost thereof. This trend is particularly evident in the field of digital information home appliances. In order to respond to such requests from the electronic apparatus industry, the semiconductor industry has been forced to shift the keystone thereof from emories to system LSIs. A system LSI is practically implemented by mounting memories and various logical circuits on one chip. Such system-on-chip implementation naturally requires process technology for enabling elements such as transistors having different structures to be formed on a common substrate. In addition, it requires great innovation in design technology.
As design technology for supporting such system-on-chip implementation, proposed is a design technique where data for designing a block composed of a plurality of cells for implementing a certain function (for example, one called a function block) is prepared beforehand, and such data is utilized to design a desired system LSI composed of a combination of such blocks. According to this technique, since the structure for implementing the function of each function block has been determined, only design of wiring between function blocks and peripheral circuits is required in the design of the entire semiconductor device. In this way, substantial improvement of design efficiency is intended.
However, the above conventional design technique only includes determining which blocks out of those obtained by lower-level design such as logic design and layout design should be used and how these blocks should be arranged and interconnected. It does not allow for flexible use of the respective blocks, such as using only some components of each block. This technique therefore may fail to fully satisfy a variety of requests directed to system LSIs such as size reduction.
SUMMARY OF THE INVENTION
In view of the above-noted problems with the prior art techniques, the present invention was made to construct a novel design system replacing the conventional design technique using blocks as described above. Specifically, an object of the present invention is to provide a database for design of an integrated circuit device where data usable for system verification is stored in a flexibly utilizable state, and a method for designing an integrated circuit device using such a database.
The database for design of an integrated circuit device according to the present invention includes a virtual core cluster including a plurality of virtual cores for storing data required for designing the integrated circuit device, the virtual core cluster being arranged in a hierarchical structure of a plurality of layers according to the levels of abstraction. The database further includes, for a target integrated circuit device to be designed and the other integrated circuit device that performs signal transmit/receive behavior with the target integrated circuit device, a test cluster for storing data required for verifying the function of the virtual cores and the function of a system constructed using the virtual cores, the test cluster being arranged in a hierarchical structure of the same number of layers as the virtual core cluster in correspondence with the respective hierarchical layers of the core cluster.
In the above database for design of an integrated circuit device, the test cluster preferably includes at least one of a test bench, a test scenario, a task, and a model.
The database for design of an integrated circuit device may further include a system verification database for verifying a system when the integrated circuit device is constructed by combining the virtual cores, the system verification database being arranged in a hierarchical structure of the same number of layers as the virtual core cluster in correspondence with the respective hierarchical layers of the virtual core cluster. In this case, the test cluster may be located in the system verification database.
The test cluster may be linked to the virtual core cluster.
In the database for design of an integrated circuit device, the virtual core cluster may include: specification/behavior virtual cores for storing data in specification/behavior levels required for constructing the integrated circuit device; and register transfer virtual cores for storing data in a function level required for satisfying the specification/behavior specified by the data stored in the specification/behavior virtual cores. In this case, the test cluster is arranged in a hierarchical structure of a specification layer, an behavioral layer, and a function layer.
In the above case, the test cluster may include in the specification layer a description relating to the input/output relationship between the target integrated circuit device and the other integrated circuit device that performs signal transmit/receive behavior with the target integrated circuit device.
In the case where the test cluster is located outside the virtual core cluster for the target integrated circuit device, the test cluster may include in the behavioral layer a description for generating data for activating a sequence in the behavioral layer of the virtual core cluster for the target integrated circuit device. This makes it possible to automatically verify the behavioral layer for the target integrated circuit device. In the above case, also, the test cluster may include in at least one of the behavioral layer and the function layer a description for receiving results of a sequence in the behavioral layer of the virtual core cluster for the target integrated circuit device. This makes it possible to further ensure the verification in the behavioral layer for the target integrated circuit device.
In the case where the test cluster is located inside the virtual core cluster for the target integrated circuit device, the test cluster may include in the function layer a description for controlling a sequence in the behavioral layer of the virtual core cluster for the target integrated circuit device.
The method for designing an integrated circuit device according to the present invention is a method for designing an integrated circuit device using a database for design. The database for design includes a plurality of virtual core clusters each including a plurality of virtual cores for storing data required for designing the integrated circuit device, each of the virtual core clusters being arranged in a hierarchical structure of a plurality of layers according to the levels of abstraction. The database further includes, for a target integrated circuit device to be designed and the other integrated circuit device that performs signal transmit/receive behavior with the target integrated circuit device, a test cluster for storing data required for verifying a system when the integrated circuit device is constructed by combining virtual cores in the virtual core clusters, the test cluster being arranged in a hierarchical structure of the same number of layers as the virtual core cluster in correspondence with the respective hierarchical layers of the virtual core cluster. The method includes the step of: when verification is performed for one layer among the plurality of layers of the virtual core cluster for the target integrated circuit device, perform
Fujiwara Makoto
Takemura Kazuyoshi
Do Thuan
McDermott & Will & Emery
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