Data writing method for semiconductor memory device and...

Details Data writing method for semiconductor memory device and... Data writing method for semiconductor memory device and...

2002-02-20

2004-10-26

Nguyen, Van Thu (Department: 2824)

Static information storage and retrieval

Floating gate

Particular biasing

C365S230030

Reexamination Certificate

active

06809967

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Applications No. 2001-043643, filed Feb. 20, 2001; and No. 2002-038244, filed Feb. 15, 2002, the entire contents of both of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device. More specifically, the present invention relates to a data writing method for a nonvolatile semiconductor memory device capable of decreasing the disturbance of the data due to capacitance coupling even if the distance between adjacent memory cells becomes narrow, and the nonvolatile semiconductor memory device.
2. Description of the Related Art
A nonvolatile semiconductor memory to read the information, has been developed, in such a manner that an electric charge, which is injected from a channel to an charge accumulation layer through a tunnel insulation film by a tunneling current, is used as information storage of a digital bit and the conductance change of MOSFET in accordance with its electric charge amount is measured. However, according to a constitution of a conventional nonvolatile semiconductor memory and a conventional writing method, in concurrence with high accumulation of a memory cell, the capacitance coupling between the charge accumulation layers of the memory cells is increased, so that this involves a problem such that the data of the adjacent memory cells is disturbed dependent on an order of writing. First, a problem in a conventional example will be explained with reference to
FIGS. 37
to
43
.
FIG.
38
A and
FIG. 38B
illustrate circuit diagrams of a cell block of a conventional NAND type and a cell block of a conventional AND type EEPROM.
In FIG.
38
A and
FIG. 38B
, reference numerals MO to M
15
and M
0
′ to M
15
′ denote memory cells and reference numerals
49
and
49
′ respectively denote one memory cell block to be formed, for example, by a NAND type block and an AND type block. A plurality of data selection lines (WL
0
to WL
15
) is connected to one memory cell block
49
,
49
′. Alternatively, memory cell block selection lines SSL and GSL are connected to the memory cell block
49
. Further, reference numerals BL
1
and BL
2
denote data transfer lines and they are arranged in a direction mutually orthogonal to the data selection line (not shown). Each memory cell in the memory cell block
49
is formed at an intersecting point of the data transfer line and the data selection line. In each memory cell, it is possible to data store and data read, independently. In this case, assume a memory cell is a transistor having, for example, a charge accumulation layer and representing data by the electric charge amount of its charge accumulation layer. These plural memory cell blocks
49
are formed in a direction of the data transfer line and in a direction of the data selection line to form a memory cell array
1
.
FIG. 39
illustrates a layout example of a memory cell array
1
and a sense amplifier
46
according to a conventional example including a sense amplifier circuit. In
FIG. 39
, in order to make the drawing understandable, the data selection lines WL
0
to WL
15
and the block selection lines SSL and GSL are omitted.
In
FIG. 39
, reference numerals BL
1
x
, BL
2
x
(x=a, b, c . . . k) denote data transfer lines. The memory cell blocks
49
and
49
′ shown in
FIG. 38
are connected to the data transfer lines, respectively and the data transfer lines are connected to one sense amplifier x via Q
1
x
and Q
2
x
. The subscripts such as a, b, . . . k are indices which are attached conveniently for representing plural lines of memory cell layouts and a total number of the indices may be any number if it is a plural number. In other words, the sense amplifier needs a transistor larger than one memory cell, so that one sense amplifier
46
is shared by a plurality of data transfer lines so that an area occupied by the sense amplifier is contracted. Further, the sense amplifier
46
serves to read the data of the memory cell and it doubles with a data register, which temporally keeps data to be written in the memory cell. Further, this sense amplifier
46
is commonly connected to data lines I/O and I/OB for connecting writing and the reading data to a data input/output buffer
45
, respectively. Following a general rule, a direction along the data selection line is referred to as a row and a direction along the data transfer line is referred to as a column below.
In the case of writing data in the memory cell M
1
′ of the memory cell block
49
′ in the conventional circuit of
FIG. 38
, the data transfer line BL
2
connected to the sense amplifiers is biased, for example, in such a manner that the output voltage of the data register takes a voltage value in accordance with the written data. At the same time, a program voltage Vpgm having a potential difference which is sufficiently larger than the potential of the data transfer line which writes the data is pulsed in time to a sufficient extent for injecting a carrier to be applied to the data selection line WL
1
in such a manner that the sufficiently high voltage is applied so that the current flows through the tunnel insulation film of a nonvolatile memory element of the memory cell. In this case, it is necessary that the data of M
1
′ should not written in the memory cell block
49
adjacent to the memory cell block
49
′. Further, it is also necessary that the data of M
1
′ should not written in the memory cell M
0
′ adjacent to M
1
′. Alternatively, according to the conventional example, these memory cells M
0
′, M
1
′ and M
1
are connected to one sense amplifier
46
, so that it is not possible to write arbitrary data in a plurality of memory cells connected to one sense amplifier.
Next,
FIG. 40
shows a writing sequence according to the conventional example, in which a problem occurs.
FIG. 40
illustrates a flowchart for independently writing data, for example, in the memory cells M
1
and M
1
′ belonging to two adjacent columns. The present example is formed on the same well. In the present example, it is supposed that a flash memory in which the data is entirely deleted. Further, in the present example, it is supposed that an initial state of the memory cell is a state that all data are “11”, namely, a state that the negative accumulated electric charge in the charge accumulation layer is most decreased. In a constitution of the conventional example, according to a procedure for writing data in a cell at a first column connected to BL
1
, at first, the written data is latched in a data register of the sense amplifier
46
through an I/O and an I/OB and then, a step (SE
120
) is performed to determine whether or not the data are sufficiently written in all memory cells at the first column in such a manner that the written data at the first column is written, the data at the first column is read and a determination result of a threshold voltage of the written memory cell is stored in the data register of the sense amplifier
46
. Hereby, it is possible to form, for example, a threshold voltage distribution of the memory cell M
1
′ as shown by a broken line in FIG.
41
. According to the custom, it is assumed that four threshold distributions correspond to values of “11”, “10”, “00” and “01” in sequence from a distribution in which the threshold voltage is lower.
Next, the arbitrary data of “11”, “10”, “00” and “01” is written in the adjacent memory cell M
1
in a row direction (SE
121
). Hereby, a negative electric charge of the charge accumulation layer of M
1
is increased in accordance with the value of each data. In this case, if the negative electric charge of the charge accumulation layer of M
1
is increased, its voltage rises. In this case, the charge accumulation layer lies in an electrically floating state, so that a voltage of the charge accu

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