Electrical computers and digital processing systems: memory – Storage accessing and control – Specific memory composition
Reexamination Certificate
2008-03-12
2011-10-25
Farrokh, Hashem (Department: 2188)
Electrical computers and digital processing systems: memory
Storage accessing and control
Specific memory composition
C365S185030
Reexamination Certificate
active
08046528
ABSTRACT:
A data writing method for a block of a multi level cell NAND flash memory including upper page addresses and lower page addresses is provided, wherein a writing speed at the lower page addresses is higher than that at the upper page addresses. The data writing method includes receiving a writing command and determining whether an address to be written with new data in the writing command is the upper page address of the block. The method also includes copying old data previously recorded on the lower page addresses of the block as an old data backup when the address to be written in the writing command is the upper page address of the block and then writing the new data to the address to be written. Thus, old data may be protected while writing data to the upper page address of the multi level cell NAND flash memory.
REFERENCES:
patent: 7639531 (2009-12-01), Cornwell et al.
patent: 2006/0126394 (2006-06-01), Li
patent: 2006/0155921 (2006-07-01), Gorobets et al.
patent: 2007/0245098 (2007-10-01), Takada
patent: 2008/0002467 (2008-01-01), Tsuji
Chu Chien-Hua
Teo Wei-Chen
Farrokh Hashem
J.C. Patents
Phison Electronics Corp.
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