Data writing circuit for a nonvolatile semiconductor memory

Details Data writing circuit for a nonvolatile semiconductor memory Data writing circuit for a nonvolatile semiconductor memory

1997-08-27

1999-06-08

Nelms, David

Static information storage and retrieval

Read/write circuit

36518516, 36518905, 36518529, 365218, G11C 1604

Patent

active

059109181

ABSTRACT:
A data writing circuit includes: a transfer gate (TG) selecting a bit line (BL0) of a virtually grounded cell array; a latch circuit (L) connected to the bit line (BL0) via the transfer gate (TG) for latching the data to be written, given to the bit line; a switching circuit (PM) which is connected between the bit line (BL0) and a program power source (VFROG) and is activated in accordance with the data to be written which has been latched by the latch circuit (L), to thereby supply the program power source (V.sub.PROG) to the bit line (BL0). This circuit, in accordance with the data to be written, sets the bit line (BL0) to which a memory cell (M) is connected, to a state of being applied by the program power source (V.sub.PROG) or a floating state.

REFERENCES:
patent: 5051956 (1991-09-01), Burns
patent: 5465235 (1995-11-01), Miyamoto
patent: 5473563 (1995-12-01), Suh et al.
patent: 5541879 (1996-07-01), Suh et al.
patent: 5751634 (1998-05-01), Itoh
Kobayashi, et al., "Memory Array Architecture and Decoding Scheme for 3V Only Sector Erasable DINOR Flash Memory" IEEE J. of Solid-State Circuits 29(4):454-460 (1994).
Kobayashi, et al., "A 3.3V Only 16Mb DINOR Flash Memory" Inst. of Electronics, Information and Communication Engineers, ICD95-38: 55-62 (1995). (Abstract only in English).

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