Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2000-03-23
2001-04-17
Nelms, David (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S185330, C365S236000
Reexamination Certificate
active
06219289
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a data writing apparatus, a data writing method and a tester which write data to an electric device such as a semiconductor device, and more particularly, to a data writing apparatus, a data writing method and a tester which write data to a plurality of electric devices.
2. Description of Related Art
A conventional tester for testing semiconductor devices such as memory, CPU and the like have a measurement functionality for testing the multiple same semiconductor devices simultaneously. In the conventional tester with such a functionality, an electric test is performed by inputting the same data to the same pin of the devices under testing.
FIG. 1
illustrates the structure of the conventional tester. The tester
100
comprises a pattern generator
101
, a pin data selector
103
, a waveform formatter
105
and a device contactor
107
. The pattern generator
101
comprises an algorithmic pattern generator (ALPG)
109
, an address selector
111
, a pattern memory
113
and an selector
114
. The algorithmic pattern generator
109
outputs control signals and address signals according to given rules. Furthermore, ALPG
109
can output data according to given rules. The address selector
111
selects an address of the pattern memory
113
, according to the address signal from the algorithmic pattern generator
109
. The pattern memory
113
stores data to be written to each device under testing (DUT), and outputs data corresponding to the address selected by the address selector
111
. The selector
114
selects data output from the ALPG
109
or the pattern memory
113
and outputs the data to the pin data selector
103
.
The pin data selector
103
comprises a WE (write enable) pattern selector
115
, an address pattern selector
117
and a data pattern selector
119
. The WE pattern selector
115
selects an WE pattern from the control signals being output by the pattern generator
101
and outputs the pattern to the waveform formatter
105
. The address pattern selector
117
selects an address pattern from the address signals being output by the pattern generator
101
and outputs the pattern to the waveform formatter
105
. The data pattern selector
119
selects data being output by the pattern memory
113
in the pattern generator
101
or the ALPG
109
, and outputs data to the waveform formatter
105
.
The waveform formatter
105
comprises a WE pattern formatter
121
, an address pattern formatter
123
and a data pattern formatter
125
. The WE pattern formatter
121
formats the waveform of the WE pattern into a given format and outputs the pattern to the input terminals of the device contactor
107
to which the pins of DUTs to receive the WE pattern contact. The address pattern formatter
123
formats the waveform of the address pattern into a given format and outputs the pattern to the input terminals of the device contactor
107
to which the pins of DUTs to receive the address pattern contact. The data pattern formatter
125
formats the waveform of the data pattern into a given format and outputs the pattern to the input terminals of the device contactor
107
to which the pins of DUTs to receive the data pattern contact. The device contactor
107
enables each pattern being output from the waveform formatter
105
to be input to the specific pins of multiple DUTs which contacs to the device contactor
107
.
In this tester, the ALPG
109
in the pattern generator
101
outputs control signals and address, and the ALPG
109
or the pattern memory
113
outputs data to be written to DUTS. Then, the pin data selector
103
selects the patterns stated above from control signals, addresses and data, and outputs the patterns to the waveform formatter
105
. The waveform formatter
105
formats each of the patterns into a given format and inputs it to the specific pins of DUTs which contact to the device contactor
107
simultaneously via the device contactor
107
. Therefore, the same data can be written into a plurality of the same DUTs.
Recently, semiconductor devices, such as a flash memory, an LSI (Large-scale integrated circuit) having flash memories, a CPU (central processing unit) and the like, have a unique identification information to distinguish between the devices. For this reason, it is necessary to write different information for each of the devices, even though for the same type of devices.
To better explain the problem of the conventional tester, assume that different information is written to each of semiconductor devices, using the above conventional tester. If the pattern memory
113
stores data to be written to each one of DUTs, the conventional tester can output different data for each one of DUTs. However, if multiple DUTs contact to the device contactor
107
, the same data will be written to the multiple DUTs. Therefore, in order to write different data for each one of DUTs, for instance, only a DUT to which data is written must contact to the device contactor
107
, while other DUTs must be released from the device contactor
107
.
FIG. 2
illustrates the timing chart when different data is written to each one of DUTs, using the conventional tester.
FIG. 2
is the timing chart when different data is written to each one of flash memories as an example of DUT. The flash memory herein inputs to the specific pin the supplied program as a control signal to execute a write command when a write enabling signal is active (low in this example), then writes the supplied data to the supplied address of the flash memory, when a write enabling signal is active. Furthermore, the flash memory confirms the completion of writing data by polling.
As shown in
FIG. 2
, the conventional tester must execute the data writing process to DUT#
2
after completing the data writing process to DUT#
1
. Thus, the data writing process for each one of DUTs must be executed sequentially. Therefore, it yields a problem that it takes a long time to write different data into multiple DUTs.
On the other hand, assuming writing different data simultaneously to each one of DUTs, it is necessary to provide the structure for simultaneously generating multiple test patterns to be input to each one of DUTs, and also provide multiple signal paths to input each test pattern to each one of DUTs. As a result, the tester becomes larger in scale and costs more.
SUMMARY OF THE INVENTION
Therefore, it is an object of the present invention to overcome these drawbacks in the prior art, and to provide a data writing apparatus, a data writing method, and a tester to write data to a plurality of electric devices easily and in a short time. This object is achieved by combinations described in the independent claims. The dependent claims define further advantageous and exemplary combinations of the present invention.
In order to achieve the object, a data writing apparatus according to the first embodiment of the present invention is a data writing apparatus for writing data to a plurality of electric devices, comprising: a data storing unit which stores a plurality of the data to be written to at least one of the electric devices; a data generating unit which outputs the plurality of the data sequentially from the data storing unit; a data sequence number storing unit which stores sequence numbers, each indicating at least one of the electric devices; a counter which counts times of the data being output sequentially from the data generating unit; and a data writing control unit which enables one of the electric devices indicated by the sequence number that is equal to the times counted by the counter, to write the data.
The data writing apparatus may further comprise a sequence number setting unit which sets the sequence number to the data sequence number storing unit. The data generating unit may output the data sequentially according to a given base clock; and the counter may count times of the data being output sequentially according to the base clock.
The data writing apparatus may further comprise a
Satoh Kazuhiko
Tsuchida Shigeo
Advantest Corporation
Lam David
Nelms David
Pillsbury & Winthrop LLP
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