Data writing and reading method for a frame memory having a plur

Details Data writing and reading method for a frame memory having a plur Data writing and reading method for a frame memory having a plur

1997-02-12

1999-04-20

Swann, Tod R.

Electrical computers and digital processing systems: memory

Address formation

Generating a particular pattern/sequence of addresses

711217, 711 5, G06F 1206

Patent

active

058955020

ABSTRACT:
A data writing and reading method for a frame memory which provides a high speed data access by using a memory which is divided into a plurality of portions each of which has a plurality of banks. The frame memory stores sets of data corresponding to an image to be displayed on a screen of a display unit. A set of data is written in one of the banks of one of the frame memory portions in accordance with two-dimensional accessing. Then another set of data is written in another one of the banks of one of the frame memory portions when that one of the memory portions is next accessed. The sets of data written in the frame memory is read in accordance with one-dimensional accessing.

REFERENCES:
patent: 5142276 (1992-08-01), Moffat
patent: 5598517 (1997-01-01), Watkins
patent: 5717441 (1998-02-01), Serizawa et al
patent: 5758128 (1998-05-01), Larson

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