Data write circuit in memory system and data write method

Details Data write circuit in memory system and data write method Data write circuit in memory system and data write method

2003-05-13

2004-11-23

Nguyen, Tan T. (Department: 2818)

Static information storage and retrieval

Read/write circuit

Flip-flop used for sensing

C365S190000, C365S189011

Reexamination Certificate

active

06822917

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2002-138485, filed May 14, 2002, the entire contents of which are incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a memory system such as a DRAM which amplifies a low-level signal stored in a memory cell to read information, particularly to a data write circuit in the memory system, and a data write method.
2. Description of the Related Art
In a memory system such as DRAM, a low-level signal stored in a memory cell is amplified and information (data) is read. With an increase of the number of memory cells by a large capacity of a memory, a bit line capacitance as a node in which a sense amplifier senses data increases, and a capacitive coupling between bit lines increases. The increase of the bit line capacitance or capacitive coupling adversely affects a sense operation essential for high speed of a random cycle, and a peripheral operation. Examples of this adverse influence include a drop of sense speed or restore speed of the DRAM, and an increase of disturbance at a write time. The drop of speed and the increase of disturbance become obstacles in construction a high-speed cycle memory system. Especially in recent years, the high-speed cycle memory system has increasingly played an important role for a relay system of data transfer in a network.
Next, the bit line capacitance, and the influence of the capacitance between the bit lines with respect to the sense operation will be described.
As shown in
FIG. 1
, a bit line pair BL
2
, /BL
2
to be noticed, and bit line pairs BL
1
, /BL
1
and BL
3
, /BL
3
disposed on opposite sides of the pair will be considered. A bit-line capacitance Cb of the bit line pair BL
2
, /BL
2
is represented by: Cb=C+Cbb, wherein Cbb denotes a coupling capacitance of the bit line pair BL
2
, /BL
2
with the bit lines /BL
1
, BL
3
(adjacent bit lines) disposed on the opposite sides of the pair, and C denotes another capacitance.
Here, data exists so that, for example, “0” is sensed in the noticed bit line pair BL
2
, /BL
2
. In this case, the bit line BL
2
changes to a low potential level, and the bit line /BL
2
changes to a high potential level. In the bit line pairs BL
1
, /BL
1
and BL
3
, /BL
3
disposed on the opposite sides of the noticed bit line pair BL
2
, /BL
2
, “1” or “0” is sensed/amplified.
At this time,
FIG. 2A
shows a state of an ideal potential change of the bit line pair BL
2
, /BL
2
in a case in which the coupling is assumed not to exist. When a word line WL rises to a high potential level, data “0” of the memory cell is outputted onto the bit line BL
2
, and a sense operation is performed by a sense amplifier, the potential of the bit line BL
2
largely changes to a power supply potential V
SS
from an intermediate potential, and the potential of the bit line /BL
2
largely changes toward a power supply potential V
DD
.
Moreover, the potential changes of the bit line pairs BL
1
, /BL
1
and BL
3
, /BL
3
disposed adjacent to the noticed bit line pair BL
2
, /BL
2
are assumed as follows. The bit line BL
1
changes to a low level, and the bit line /BL
1
changes to a high level. The bit line BL
3
changes to the low level, and the bit line /BL
3
changes to the high level. Then, by a coupling capacitance Cbb, as shown in
FIG. 2B
, from the ideal state shown by a broken line, the potential changes of the bit line pair BL
2
, /BL
2
are suppressed as shown by a solid line. Therefore, time is unnecessarily required until the bit line pair BL
2
, /BL
2
reaches a sufficient restore level.
In this situation, when the capacitance can be replaced with an effective bit line capacitance Cbeff, and the adjacent bit lines /BL
1
, BL
3
change in a direction reverse to the potential changes of the noticed bit line pair BL
2
, /BL
2
, an excess charge is further required by the coupling. As a result, the effective bit line capacitance Cbeff is represented by:
Cbeff=C+
2
Cbb=Cb+Cbb
That is, it follows that the bit line capacitance further increases by “Cbb”.
When the data is read or restored from the memory cell, the bit line capacitance increases and an excess time is only required. However, when the data is written, there is possibility that an erroneous operation is caused.
FIG. 3
is a schematic explanatory view showing that “0” is written in the noticed bit line pair BL
2
, /BL
2
. In the adjacent bit line pairs BL
1
, /BL
1
and BL
3
, /BL
3
, “1” or “0” is read, sensed, and refreshed. It is assumed that the bit line BL
1
or BL
3
changes to the low level, and the bit line /BL
1
or /BL
3
changes to the high level. At this time, assuming an ideal case in which there is not any coupling between the bit line pairs, the potentials of the adjacent bit line pairs BL
1
, /BL
1
and BL
3
, /BL
3
change as shown in FIG.
4
A. That is, a low-level signal (potential) read from the memory cell is rapidly amplified at a timing tS in response to the operation of the sense amplifier, and stored information of the memory cell is refreshed.
On the other hand, when the capacitance between the bit lines is large, and there is the coupling of the potential change, the potential changes as shown in FIG.
4
B. It is assumed that “0” is forcedly written in the noticed bit line pair BL
2
, /BL
2
from the outside. At this time, the bit line /BL
2
changes to the high level, and the bit line BL
2
changes to the low level. In this case, when the data is transferred from the outside in a stage as early as possible, the write can be performed at a high speed.
However, when the data is transferred from the outside in this early stage, the micro read potentials from the memory cells in the adjacent bit line pairs BL
1
, /BL
1
and BL
3
, /BL
3
are reversed by the coupling. At a sense start time, the sense operation is performed at the potential generated by the coupling, not the read potential from the memory cell. As a result, an erroneous sense is caused with respect to the adjacent bit line pairs BL
1
, /BL
1
and BL
3
, /BL
3
.
To solve the problem, when the sense operation of the adjacent bit line pairs BL
1
, /BL
1
and BL
3
, /BL
3
sufficiently proceeds, and the sense operation is not reversed any more by the coupling, the forced write needs to be performed with respect to the noticed bit line pair BL
2
, /BL
2
. However, in this case, the excess time is required for the write, and the data cannot be written, immediately after a word line WL is raised to the high level and the memory cell is selected.
Additionally, for data transfer via a high-speed network, it has increasingly become important to perform a random cycle at a high speed, and a system referred to as late write has been employed.
FIG. 5
is a schematic diagram showing an outline of specifications of the late write system. The DRAM includes cycles of write and read, and the order in which these cycles are generated is totally random.
FIG. 5
shows these cycles along a time axis time, and address and data accessed at this time in each cycle are combined/shown. It is imaged that the data is taken into the memory by an arrow directed into a block at a write time, and it is imaged that the data is outputted from the memory by an arrow directed to the outside from the block at a read time.
In the late write operation, the taken data to be written is not transferred to the memory cell in the cycle, and the address and data are temporarily stored in a portion (register) other than the memory cell. In
FIG. 5
, an address Add
1
and data Data
1
are held in the register. The held address Add
1
and data Data
1
are transferred to the memory cell in a write cycle which soon comes next. In this manner, the address and data in the previous write cycle are transferred to the memory cell in the cycle at the present time. Since the address of a transfer destination is already known, the transfer operation can be started without waiting

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