Data write circuit

Details Data write circuit Data write circuit

2002-07-01

2003-05-20

Lebentritt, Michael S. (Department: 2824)

Static information storage and retrieval

Read/write circuit

With shift register

C365S189011, C365S230060

Reexamination Certificate

active

06567320

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to data write circuits that write data to semiconductor memories, in particular to data write circuits that are capable of writing data in prescribed units of bits, which differ from the units of bits originally employed in computers and digital signal processors (DSP), for example.
2. Description of the Related Art
Recently, small-size computers such as personal computers normally have central processing units (CPU) that operate in prescribed units of bits, such as thirty-two two bits. Hence, semiconductor memories installed in computers perform read/write operations in prescribed units of bits, such as thirty-two bits. Conventionally, however, there exist numerous software programs that perform read/write operations in units of bytes (eight bits). For this reason, conventional software programs require circuits that enable accessing memories in units of bytes under the control of 32-bit CPUs.
FIG. 11
is a block diagram showing a typical example of a circuit configuration having a byte-accessing capability under the control of a 32-bit CPU. Herein, reference numeral
1
designates a 32-bit CPU; reference numerals
2
a
to
2
d
designate static random-access memories (SRAMs) that perform read/write operations in units of bytes; reference numeral
3
designates a control circuit that realizes accessing in units of bytes. The CPU
1
provides 32-bit address data, which is designated by A(
31
:
00
) wherein the number ‘31’ in the left side of the parentheses designates bit
31
within thirty-two bits, and the number ‘00’ in the right side of the parentheses designates bit
0
of thirty-two bits. Herein, the lowermost two bits, namely bit
0
and bit
1
of the 32-bit address data A(
31
:
00
) are supplied to the control circuit
3
, and the other bits, namely address data A(
31
:
02
) ranging from bit
2
to bit
31
, are commonly supplied to address terminals a(n:
0
) of the SRAMs
2
a
to
2
d
. The SRAM
2
a
has an input terminal i(
7
:
0
) and an output terminal o(
7
:
0
), both of which are arranged for the first byte ranging from bit
0
to bit
7
of the 32-bit data of the CPU
1
. Similarly, the SRAM
2
b
has an input terminal i(
15
:
8
) and an output terminal o(
15
:
8
), both of which are arranged for the second byte ranging from bit
8
to bit
15
; the SRAM
2
c
has an input terminal i(
23
:
16
) and an output terminal o(
23
:
16
), both of which are arranged for the third byte ranging from bit
16
to bit
23
, and the SRAM
2
d
has an input terminal i(
31
:
24
) and an output terminal o(
31
:
24
), both of which are arranged for the fourth byte ranging from bit
24
to bit
31
. The aforementioned input terminals and output terminals of the SRAMs
2
a
to
2
d
are respectively connected with data terminals D(
31
:
00
) for 32-bit data ranging from bit
0
to bit
31
, as follows:
SRAM
2
a
: both the input terminal and output terminal are connected together with data terminals for the first byte ranging from bit
0
to bit
7
of the 32-bit data of the CPU
1
.
SRAM
2
b
: both the input terminal and output terminal are connected together with data terminals for the second byte ranging from bit
8
to bit
15
of the 32-bit data of the CPU
1
.
SRAM
2
c
: both the input terminal and output terminal are connected together with data terminals for the third byte ranging from bit
16
to bit
23
of the 32-bit data of the CPU
1
.
SRAM
2
d
: both the input terminal and output terminal are connected together with data terminals for the fourth byte ranging from bit
24
to bit
31
of the 32-bit data of the CPU
1
.
In addition, the CPU
1
also provides to the control circuit
3
a signal VA that designates either a byte access mode or a word (32 bits) access mode.
In the aforementioned circuit configuration shown in
FIG. 11
, the CPU
1
provides a signal VA of ‘0’ to the control circuit
3
in order to perform write operations in units of words. In this case, the CPU
1
supplies the address data A(
31
:
02
) to the SRAMs
2
a
to
2
d
respectively. Additionally, the CPU
1
supplies write data D(
31
:
00
) consisting of bit
0
to bit
31
in such a way that bit
0
to bit
7
are supplied to the SRAM
2
a
, bit
8
to bit
15
are supplied to the SRAM
2
b
, bit
16
to bit
23
are supplied to the SRAM
2
c
, and bit
24
to bit
31
are supplied to the SRAM
2
d
. Incidentally, the lowermost two bits, namely bit
0
and bit
1
, of the address data A(
31
:
00
) are irrelevant to the circuit operation. When the control circuit
3
detects the signal VA of ‘0’ output from the CPU
1
, it outputs write enable signals WENa to WENd to the SRAMs
2
a
to
2
d
respectively. Thus, all the write data D(
31
:
00
) output from the CPU
1
are completely written to the SRAMs
2
a
to
2
d.
The CPU
1
provides a signal VA of ‘1’ to the control circuit
3
in order to perform write operations in units of bytes. In this case, the CPU supplies the address data A(
31
:
02
) to the SRAMs
2
a
to
2
d
respectively, while it supplies address data A(
1
) and A(
0
) to the control circuit
3
. Additionally, the CPU
1
commonly supplies write data D to all the SRAMs
2
a
to
2
d
. Then, the CPU
1
supplies a write enable signal WEN to one of the SRAMs
2
a
to
2
d
, which is designated by the address data A(
0
) and A(
1
). In the case where both the address data A(
0
) and A(
1
) are set to ‘0’, for example, the CPU
1
supplies a write enable signal WENa to the SRAM
2
a
. Thus, the write data D output from the CPU
1
are written to only the SRAM
2
a.
As described above, the data write circuit having byte-accessing capability conventionally requires multiple memories in order to perform read/write operations in units of bytes. Therefore, the data write circuit performs control for each of the memories. This results in unwanted complexity in the configuration of the control circuit. In addition, the overall size of the memory chip(s) increases because of increases in the wiring regions between memories.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a data write circuit having word/byte-accessing capabilities, which is realized by a simple configuration of a control circuit with a noticeable reduction of the size of a memory chip.
A data write circuit of this invention is interposed between the CPU and memory, both of which operate based on the same number of bits (e.g., thirty-two bits). The CPU produces address data for designating a specific address in the memory, and access mode designation data for designating one of the byte access mode, half-word access mode, and word access mode. The data write circuit comprises a decoder for decoding the access mode designation data, a logic circuit for generating selection signals, and four selectors, each of which deal with 8-bit data consisting of eight prescribed bits of the original thirty-two bits. Each selector selects either first data read from the memory or second data output from the CPU.
When the access mode designation data designates the byte access mode, one of the selectors is forced to select the second data, which are substituted for the first data in the memory. That is, it is possible to replace a specific byte in the memory with new data provided from the CPU. For example, only the low-order eight bits consisting of bit
0
to bit
7
are replaced with the corresponding data output from the CPU in the memory. When the access mode designation data designates the half-access mode, two of the selectors are forced to select the second data, which are substituted for the first data in the memory. That is, it is possible to replace a specific half-word in the memory by new data provided from the CPU. When the access mode designation data designates the word access mode, all the selectors are forced to select the second data, which are substituted for the first data in the memory. Thus, it is possible to entirely replace a word in the memory by new data provided from the CPU. Incidentally, it is possible to

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