Error detection/correction and fault detection/recovery – Pulse or data error handling – Transmission facility testing
Reexamination Certificate
1999-08-31
2003-04-01
Decady, Albert (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Transmission facility testing
C714S018000, C714S748000, C370S412000
Reexamination Certificate
active
06543014
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a data transmitting/receiving apparatus, and more particularly to a data transmitting/receiving apparatus having a function retransmit data in the event of the occurrence of any transfer error.
A parallel processor system in which a plurality of processing nodes are connected by a network performed retransmission, even where a transfer error occurred within the network during a data transfer between processing nodes, from the processing node on the transmitting side.
This prior art will be described more specifically below.
FIG. 9
is a block diagram illustrating the parallel processor system according to the prior art.
In this parallel processor system, N processor elements
600
(
1
) to (N), each having a data transferring apparatus
608
provided with a data transmitting apparatus
300
and a data receiving apparatus
400
are connected to one another via an interconnecting network
700
.
In
FIG. 9
, each of the processor elements
600
(
1
) to (N) has a processor
602
, a memory
604
, an internal bus
606
and a data transferring apparatus
608
for data communication with other processor elements. Between the data transferring apparatuses
608
of the processor elements
600
(
1
) to (N) and the interconnecting network
700
are provided external buses
612
(
1
) to (N), respectively.
Suppose that a transfer error arises within the interconnecting network
700
in this parallel processor system when data are transferred from the processor element
600
(
1
) to the processor element
600
(N) for instance. Then, on the basis of the actions of the data transmitting apparatus
300
and the data receiving apparatus
400
to be described below, the destination processor element
600
(N) detects a reception error ensuing from this transfer error, and a retransmission request signal is transmitted from the data transferring apparatus
608
in the processor element
600
(N) to the processor element
600
(
1
). The processor element
600
(
1
), upon receipt of the retransmission signal, temporarily interrupts its transfer processing, and retransmits the data in which the transfer error arose from the data transferring apparatus
608
in the processor element
600
(
1
).
FIG. 7
shows a block diagram of the data transmitting apparatus
300
and the data receiving apparatus
400
the data transferring apparatus
608
in a processor element
600
is equipped with. Whereas these apparatuses, provided in the data transferring apparatus
608
of each processor element, transmit and receive data, the description with reference to
FIG. 7
supposes that the data transmitting apparatus
300
and the data receiving apparatus
400
are provided in separate processor elements, and data transfers are performed between them.
The data transmitting apparatus
300
is provided with a FIFO memory
302
, a FIFO control circuit
304
, an ECC circuit
306
, a data latch
308
, a data selector
310
and a data transmission control circuit
312
. And the data transmitting apparatus
300
successively transmits data
16
and, any error is detected of the transmitted data in the data receiving apparatus
400
, receives a retransmission request signal
18
returned from the data receiving apparatus
400
.
On the other hand, the data receiving apparatus
400
is provided with a data receiving circuit
402
equipped with a data latch
404
and an ECC circuit
406
, a FIFO memory
408
, a FIFO control circuit
410
and a data reception control circuit
412
. Of these, the data latch
404
is a circuit for receiving the data
16
from the data transmitting apparatus
300
.
When performing data transmission, the data transmission control circuit
312
in the data transmitting apparatus
300
gives an instruction to the FIFO control circuit
304
to have a datum taken out of the FIFO memory
302
. And it causes the data selector
310
to select the datum that has been taken out and to transmit them as the data
16
, and causes the data latch
308
to hold that datum. The data transmission control circuit
312
in this manner causes a certain datum (datum n+1) and, having this datum held by the data latch
308
, causes the FIFO control circuit
304
to take out the succeeding datum (datum n+2) from the FIFO memory
302
and the data selector
310
to transmit it. After that, it judges the presence or absence of a retransmission request signal for the earlier transmitted datum n+1.
If it finds, as a result of judgment, that no retransmission request signal
18
for the datum n+1 has been received, it has the datum n+2 held by the data latch
308
, and updates the datum n+1 held within the data latch until then. And it causes the FIFO pointer of the FIFO control circuit
304
to be updated. After that, it causes the FIFO control circuit
304
to take out the succeeding datum (datum n+3) from the FIFO memory
302
and the data selector
310
to transmit this datum n+3, thereby executing a series of consecutive data transmitting actions.
On the other hand, if it finds, as a result of judgment, that a retransmission request signal
18
for the datum n+1 has been received, it causes the data latch
308
to keep the datum n+1 instead of holding the data n+2, and forbids the FIFO control circuit
304
from updating the FIFO pointer. And it executes the retransmitting action of causing the data n+1, held by the data latch
308
, to be transmitted to the data selector
310
as the retransmit datum.
When receiving data, the data reception control circuit
412
in the data receiving apparatus
400
causes the data receiving circuit
402
to receive data sent from the data transmitting apparatus
300
. And it causes the data outputted from the data receiving circuit
402
to be stored into the FIFO memory
408
.
The data reception control circuit
412
, after having a certain datum (datum n+1) stored into the FIFO memory
408
in this manner, causes the next datum sent from the data transmitting apparatus
300
to be received by the data latch
404
. After that, it judges the generation or non-generation of an error detection signal
17
for the datum n+1 by the ECC circuit
406
. In this process, the FIFO pointer of the FIFO control circuit indicates the area into which the datum n+1 was stored out of all the areas of the FIFO memory
408
.
If it is found, as a result of judgment, that no error detection signal
17
for the datum n+1 has been generated, the FIFO pointer of the FIFO control circuit
410
is updated. And the ECC circuit
406
is caused to execute checking and outputting of the datum n+2, and the datum n+2 outputted from the ECC circuit
406
is stored into the FIFO memory
408
. After that, a series of consecutive data receiving actions to have the next datum (datum n+3) transferred from the data transmitting apparatus
300
received by the data latch
404
are executed.
On the other hand, if it is found, as a result of judgment, that an error detection signal
17
for the datum n+1 has been generated, a retransmission request signal
18
is transmitted to the data transmitting apparatus
300
. At the same time, the pointer of the FIFO control circuit
410
is forbidden from being updated so as to have the datum n+1 stored in the FIFO memory
408
discarded, and checking and outputting of the already received datum n+2 by the ECC circuit
406
are also forbidden so as to discard it. And the retransmit datum, sent from the data transmitting apparatus
300
, is caused to undergo execution of reception, checking and outputting by the data receiving circuit
402
. After that, a re-receiving action to store the retransmit datum, outputted from the data receiving circuit
402
, into the FIFO memory
408
on the basis of the FIFO pointer, which is locked as stated above, is executed.
FIG. 8
is a time chart showing the actions of the data transmitting apparatus
300
and the data receiving apparatus
400
as described above.
In the data
Miyaki Miki
Nunogawa Koji
Okuyama Tsuyoshi
Britt Cynthia
De'cady Albert
Hitachi , Ltd.
Mattingly Stanger & Malur, P.C.
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