Data transmission error reduction via automatic data...

Details Data transmission error reduction via automatic data... Data transmission error reduction via automatic data...

2006-08-22

2009-10-06

Patel, Nitin C (Department: 2116)

Electrical computers and digital processing systems: support

Clock, pulse, or timing signal generation or analysis

C713S400000, C713S401000, C713S503000, C713S600000

Reexamination Certificate

active

07600144

ABSTRACT:
A data transmission error reduction circuit is formed including a delay circuit, a detection circuit and a control circuit. In one embodiment, the delay circuit includes n delay element and multiplexor pairs, selectively employable to apply an aggregate amount of time delay to a data signal. The detection circuit includes circuit elements to detect a critical reference time distance between a reference point of a data signal and at least a selected edge of a clock signal being smaller than a desired threshold. The control circuit includes circuit elements to dynamically control the aggregate amount of time delay applied by the delay circuit based at least in part on the detection of the detection circuit. In one application, m units of the data transmission error reduction circuit are correspondingly employed to reduce data transmission errors on m high speed parallel data signals of a data interface.

REFERENCES:
patent: 4820944 (1989-04-01), Herlein et al.
patent: 5481563 (1996-01-01), Hamre
patent: 5745530 (1998-04-01), Baek et al.
patent: 5831461 (1998-11-01), Dawe
patent: 5903605 (1999-05-01), Crittenden
patent: 6150863 (2000-11-01), Conn et al.
patent: 7034596 (2006-04-01), Andrews et al.
Office Action mailed Dec. 2, 2005 in U.S. Appl. No. 10/393,088.
Notice of Allowance mailed Mar. 29, 2006 in U.S. Appl. No. 10/393,088.

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