Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital data error correction
Reexamination Certificate
1998-11-30
2001-06-26
Chung, Phung M. (Department: 2133)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital data error correction
C375S225000
Reexamination Certificate
active
06253346
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transmission circuit having a cyclic redundancy check (CRC) circuit which improves operation speed of the overall system by checking errors for safe data transmission and a data the rate control circuit of which rate control portion required for data interface has two simple counter logics to control the data rate during data interface.
2. Discussion of the Related Art
Generally, safe data transmission should be performed during data transmission. For safe data transmission, it is essential to check errors and restore errors. As a method for checking errors of transmission data, a simple and logic CRC method is used. This CRC method serially detects serial transmission data of bit unit using multistage delay and XOR gate. Various equations such as sixteenth equation and thirty-second equation and the like can be expressed depending on the amount of data analysis.
The operation of such a CRC processing circuit will be described in detail with reference to FIG.
1
.
FIG. 1
shows a typical 32-bit CRC circuit. The CRC circuit performs operation of bit unit and includes 14 adders 1 and 32 delay elements
2
.
The input of the CRC circuit is added to the output z(31) and the result thereof is inputted to z(0) and another adder. The input of the other adder is the output of the delay element
2
z(i) and this output is connected to the input of z(I+1). The polynomial for this circuit can be expressed as equation
1
.
x
32
+x
26
+x
23
+x
22
+x
16
+x
12
+x
11
+x
10
+x
8
+x
7
+x
5
+x
4
+x
2
+x+
1 <Equation 1>
If 1 byte data is inputted to the CRC circuit, each byte data is shifted by 1 bit per one clock and then is inputted to the CRC circuit. In other words, the most significant bit is inputted and then the least significant bit is serially inputted. For example, when 1 byte data is 0×01, values 0 of seven are inputted and value 1 is finally inputted.
Prior to the operation of the CRC circuit, all of the delay elements
2
z(i) are defined as an initial value 1 and then byte data is inputted to the CRC circuit after initiation.
The 32-bit CRC encoder and decoder have the same fundamental operation as each other. The encoder transfers input data plus 32-bit CRC data, that is, 32 delay elements z(i). In order to detect whether or not error has occurred during data transmission, the decoder checks whether or not the values of the 32 delay elements z(i) are all 0 when all the data including CRC data are processed in the CRC circuit.
However, in the CRC method, since the data are processed in series, operation speed of the overall system is reduced. In other words, all the data are processed in parallel in the systems except for the CRC module while the data are processed in series in the CRC circuit. This causes bottlenecks in the operation of the overall system.
Meanwhile, data rate control circuit technology is applicable to the system that require coordination which prevents data error, such as digital TV(DTV), high definition TV (HDTV), video on demand (VOD) system, video conference codec system and optical band ISDN terminal codec system. In this control technology, data rate in data transmission network, equipment or parts are inevitably changed. In addition, since MPEG-2 codec system data for ATM communication maintains variability, data rate in data transmission to network is inevitably changed.
For data interface in various applications to video, audio and multi chips, it is necessary to control data rate. At this time, for data rate coordination, additional parts and circuits such as phase locked loop (PLL) and other clock sources are required.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a data transmission circuit that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a data transmission circuit having a cyclic redundancy check (CRC) circuit which improves the operation speed of the overall system by performing CRC processing in parallel and checks errors in parallel.
Other object of the present invention is to provide a data transmission circuit having a data rate control circuit of which the rate control portion has two simple counter logics to control the data rate during data interface to simplify a data rate control circuit required for system interface.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a data transmission circuit of the present invention includes a CRC circuit which performs, in parallel, CRC processing and a data rate control circuit which controls the data rate during data interface. In the data transmission circuit of the present invention, the CRC circuit includes an operation portion for initiating a storing means which stores CRC processing results and for initiating CRC processing circuit by inputting a CRC signal, a CRC logic portion for outputting CRC processing data in response to control logic, and a latch for outputting data stored in the storing means by inputting an enable signal which is indicative of the effectiveness of the current data output from the CRC logic portion.
In another aspect, the data rate control circuit includes a K down counter for down counting the bit number of burst data, a K+A down counter for further down counting the generating position of burst data through the K down data, and an RS flip-flop for latching data request or transmission position in response to processing of the K down counter and K+A down counter.
In another aspect, the CRC circuit includes an operation portion for initiating a storing means which stores CRC processing results by inputting a reset signal and for initiating a CRC processing circuit whenever new data are processed by inputting a CRC start signal, a CRC logic portion for processing and outputting CRC processing data in response to control logic, and a latch for outputting data stored in the storing means by inputting an enable signal which is indicative of the effectiveness of the current data output from the CRC logic portion.
In another aspect, the data rate control circuit includes a K down counter for down counting the bit number of burst data, a K+A down counter for down counting generating position of burst data down counted through the K down data, and RS flip-flops for latching data request or transmission position in response to processing of the K down counter and K+A down counter.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 3885098 (1975-05-01), Dowling
patent: 5361266 (1994-11-01), Kodama et al.
patent: 5640172 (1997-06-01), Kim
patent: 5923151 (1999-07-01), Satoh
Kim Jae Dong
Kim Si Joong
Koh Jong Seog
Chung Phung M.
Korea Telecommunication Authority
Merchant & Gould P.C.
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