Data transmission circuit for data buses including feedback circ

Details Data transmission circuit for data buses including feedback circ Data transmission circuit for data buses including feedback circ

1988-06-15

1992-10-06

Gossage, Glenn

Electrical transmission or interconnection systems

Nonlinear reactor systems

Parametrons

307242, 307582, 307443, 365190, 36518905, 365203, H03K 19096, H03K 1706, H03K 17687, G11C 700

Patent

active

051534592

ABSTRACT:
An improved data transmission circuit for complementary metal oxide semiconductor (CMOS) dynamic random access memory devices having a data input buffer for converting transistor-transistor logic (TTL) input data signals to CMOS logic level true and complement data signals is described. The data transmission circuit includes a pair of transmission gates for transferring the true and complement data signals in a write cycle, a pair of inverting stages connected between respective ones of the transmission gates and true and complement input/output (I/O) bus lines for inverting data signals from the transmission gates to provide the inverted data signals to true and complement I/O bus lines in the write cycle and an equalizing stage for precharging and equalizing true and complement I/O bus lines in a precharge cycle. The data transmission circuit is characterized in that each of the inverting stages can operate under the control of a block selecting clock signal regardless of the precharging voltages of the true and complement I/O bus lines.

REFERENCES:
patent: 4433393 (1984-02-01), Oritani
patent: 4507759 (1985-03-01), Yasui et al.
patent: 4665508 (1987-05-01), Chang
patent: 4757215 (1988-07-01), Seo
patent: 4763303 (1988-08-01), Flannagan
patent: 4794567 (1988-12-01), Akatsuka
patent: 4831590 (1989-05-01), Ichinose
patent: 4858188 (1989-08-01), Kobayashi

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