Miscellaneous active electrical nonlinear devices – circuits – and – Signal converting – shaping – or generating – Having specific delay in producing output waveform
Reexamination Certificate
2001-01-19
2001-10-30
Nu Ton, My-Trang (Department: 2816)
Miscellaneous active electrical nonlinear devices, circuits, and
Signal converting, shaping, or generating
Having specific delay in producing output waveform
C327S378000
Reexamination Certificate
active
06310504
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transmission circuit for compensating variations in data transmission speed between a start and an end portion of a data line. In particular, a circuit for minimizing time delay caused by resistive/capacitive loading of the data line through which data is transmitted.
2. Brief Description of the Prior Art
In development of a semiconductor device, a main issue concerns the development of integrated semiconductor devices of minimal size and capable of operating at high-speed.
When electronic devices operate at high speed, problems associated with high speed can occur. For example, a speed difference may occur at a data line having a large load. The speed difference may be due to a time delay in resistive/capacitive (RC) loading at the start and end portions of the data line connected with a driver output in transmission of data signals. Such a variation in speed is one factor lowering overall performance of semiconductor devices.
Variations in transmission speed caused by RC loading at the start and end portions of the data line connected with a driver output in transmission of data signals will be described in accordance with FIG.
1
.
Referring to
FIG. 1
, the main data line driver
101
(hereinafter referred to as “MDL”) is a driver for transmitting data signals, and a data line
102
transmits data signals sent from the MDL driver
101
. MDL is a signal transmitted through the data line
102
, including MDLn, a signal proximal to the MDL driver
101
, and MDLf, a signal further from the MDL driver
101
. In addition, MDL is pre-charged “high”, which will be kept high by a latch part
103
. When the MDL signal is enabled low, the latch part
103
turns “off”, transmitting the MDL signal through the data line
102
. The reset part
104
generates a signal RS-MDL
1
to turn “on” a transistor Tl and pre-charge MDL “high” for a predetermined period of time after sensing that MDL is enabled low. The data line
102
connects the MDL driver
101
to a data output
105
. At this time, if the data line
102
has a large loading capacity, there may be a time delay caused by RC, causing variation in the speed between MDLn and MDLf.
FIG. 6
is a timing diagram of the signal of the circuit shown in
FIG. 1
in which a speed difference occurs between MDLn and MDLf. As shown in
FIG. 6
, there is a time delay of &Dgr;t between MDLn and MDLf. The occurrence of the speed difference as such, ultimately brings about a speed push, lowering overall performance of the semiconductor device.
A solution proposed in the prior art is shown in FIG.
2
.
FIG. 2
shows a structure of a data transmission circuit constructed to solve the aforementioned problem of the speed difference occurring in
FIG. 1. A
re-buffer
202
is used for amplifying MDL and compensating for the speed push in the first compared embodiment, thereby reducing the time delay &Dgr;t. In the data transmission circuit shown in
FIG. 2
, there is an advantage in that the speed push resulting from the difference in speed can be compensated for, improving overall performance of a semiconductor device. However, the circuit of
FIG. 2
results in a larger chip with the addition of a re-buffer to the data transmission circuit to compensate for the speed push. In other words, re-buffers are added to all the data lines, resulting in a larger chip. As a result, the re-buffers are not suitable for miniaturization of a chip, and are limitedly to products whose performance is regarded as more important than the size of a chip.
SUMMARY OF THE INVENTION
The present invention provides a solution to the aforementioned problem. An object of the present invention is to provide a data transmission circuit for compensating for a difference between data transmission speed caused by RC loading that occurs at the start and end portions of a data line having a large loading capacity connected with a driver output in transmission of a data signal.
It is an object of the present invention to provide a data transmission circuit to improve overall performance of a semiconductor device as well as the speed of data transmission through a data line by minimizing a time delay caused by RC loading of the data line.
To accomplish the aforementioned objects of the present invention, there is provided a data transmission circuit including a driver for transmitting data signals, a data line through which the first data signal sent from the driver is transmitted into the second data signal, a compensation circuit for amplifying and developing the second data signal from its first state to its second state when the first data signal sent from the driver is enabled from its first state to its second state and transmitted through the data line to be the second data signal, a reset part for generating a pre-charge control signal by sensing that the first and second data signals are enabled to the second state thereof and delaying them for a predetermined period of time, and a pre-charge circuit for pre-charging the first and second data signals to its first state by the pre-charge control signal.
REFERENCES:
patent: 4189751 (1980-02-01), Nagumo
patent: 5936441 (1999-08-01), Kurita
patent: 5949270 (1999-09-01), Saito
patent: 6057673 (2000-05-01), Okayama
Lee Jin-Ho
Suh Young-Ho
F. Chau & Associates LLP
Nu Ton My-Trang
Samsung Electronics Co,. Ltd.
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