Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1995-12-15
1998-02-03
Chin, Stephen
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
370395, H03D 324
Patent
active
057152853
ABSTRACT:
In a data transmission system having a transmission apparatus and a receiving apparatus through a network which supplies first and second network clock signals to the transmission and receiving apparatus respectively, synchronizing signal generation portions in both apparatus generate first and second periodical signals generated from the first and second network clock signals having a constant phase relation therebetween. The transmission apparatus generates time information indicating a data encoding timing according to a system clock signal of the transmission apparatus and supplies the time information in response to the first periodical signal and transmits the time information with data to be transmitted to the receiving apparatus. The receiving apparatus detects and holds the time information and uses it for controlling a PLL circuit for generating a system clock signal of the receiving apparatus such that the system clock signal of the transmission apparatus is substantially in phase with that of the receiving apparatus. When an error in the PLL circuit is larger than a controllable range, the time information is loaded into a counter in the PLL circuit. Thus, the PLL circuit operates correctly when there is a jitter of the transmitting data which occurs on packetting data in the ATM network.
REFERENCES:
patent: Re33380 (1990-10-01), Cheng-Quispe et al.
patent: 3953673 (1976-04-01), Dorward
patent: 5115451 (1992-05-01), Furlong
patent: 5479445 (1995-12-01), Kloker et al.
patent: 5493583 (1996-02-01), Cripps
patent: 5566204 (1996-10-01), Kardontchik et al.
ISO/IEC 13818-1: DIS; Jun. 11, 1994; pp., 13-16 and 98-102.
Chin Stephen
Roundtree Joseph
Victor Company of Japan Ltd.
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