Pulse or digital communications – Synchronizers – Phase displacement – slip or jitter correction
Patent
1994-11-30
1998-08-18
Chin, Wellington
Pulse or digital communications
Synchronizers
Phase displacement, slip or jitter correction
375354, 375357, 370517, 370357, 370388, 370398, 327153, 327162, 327165, H04L 2536, H04L 2540, H04L 700
Patent
active
057967954
ABSTRACT:
A network (10) includes a broadband customer service module (B-CSM) (20). The B-CSM (20) includes a plurality of feeder interface cards (FICs) (36) and optical line cards (OLCS) (38) which are coupled together through a midplane assembly (34) so that each FIC (36) couples to all OLCs (38) and each OLC (38) couples to all FICs (36) through junctor groups (68). The B-CSM (20) interfaces many OC-12 SONET feeders to many OC-12 SONET lines. Within the B-CSM (20) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency lower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics (50) where data need to be extracted from signals flowing within the B-CSM (20), a clock regeneration circuit (32) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock. A geometric compensation scheme corrects for timing skew which occurs when clocks and data are distributed to points or small areas from widely dispersed locations, and when clocks and data are distributed from points or small areas to widely dispersed locations.
REFERENCES:
patent: 4763317 (1988-08-01), Lehman et al.
patent: 4821034 (1989-04-01), Anderson et al.
patent: 4999832 (1991-03-01), Chen et al.
patent: 5033044 (1991-07-01), Williams et al.
patent: 5052025 (1991-09-01), Duff et al.
patent: 5081654 (1992-01-01), Stephenson, Jr. et al.
patent: 5115455 (1992-05-01), Samaras et al.
patent: 5268935 (1993-12-01), Mediavilla et al.
patent: 5268936 (1993-12-01), Bernady
patent: 5337334 (1994-08-01), Molloy
patent: 5339311 (1994-08-01), Turner
patent: 5367518 (1994-11-01), Newman
patent: 5416773 (1995-05-01), Gamm
patent: 5440591 (1995-08-01), Liron et al.
patent: 5452297 (1995-09-01), Hiller et al.
patent: 5461622 (1995-10-01), Bleickard et al.
patent: 5541917 (1996-07-01), Farris
patent: 5550874 (1996-08-01), Lee
patent: 5557610 (1996-09-01), Calamvokis et al.
patent: 5592477 (1997-01-01), Farris et al.
"A Wide-Band Local Access System Using Emerging-Technology Components" Lloyd R. Linnell; Jul. 1986; pp. 612-618.
"ICC '93 Geneva", Woodward, Helmes, Mussman, Walker, Ulbricht and Casey; May 1993; pp. 853-857.
"Optical Communications" ACCESS; Harry Mussman; Spring 1993; p. 23.
"Network Architectures For Digital Video Delivery Service In Mid-1990S", Bahman Amin-Salehi and Martin Kerner; 1992; pp. 1758-1762.
"An Architecture For Interactive Applications", Alexander D. Gelman and Lanny S. Smoot; 1993; pp. 848-852.
"A Two-Stage Rearrangeable Broadcast Switching Network", Gaylord W. Richards and Frank K. Hwang; 1985; pp. 1025-1035.
"Physical Design Issues For Very Large ATM Switching Systems", Young, Banwell, Cheng, Estes, Habiby, Hayward, Helstern, Lalk, Mahoney and Wilson; 1990; pp. 1590-1593.
"A New Architecture For Packaging Wideband Communication Equipment Using A 3-D, Orthogonal Edge-To-Edge Topology", Wilson; 1988; 430-43.
Chen Hung-San
Hartman Stephen P.
Mussman Harry Edward
Chin Wellington
Corrielus Jean B.
GTE Laboratories Incorporated
Suchyta Leonard C.
LandOfFree
Data transferring circuit which aligns clock and data does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Data transferring circuit which aligns clock and data, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data transferring circuit which aligns clock and data will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-1122768