Electrical computers and digital data processing systems: input/ – Input/output data processing – Direct memory accessing
Reexamination Certificate
2006-05-12
2009-06-09
Tsai, Henry W. H. (Department: 2184)
Electrical computers and digital data processing systems: input/
Input/output data processing
Direct memory accessing
C710S025000, C710S026000, C710S028000, C710S308000, C709S212000, C711S001000
Reexamination Certificate
active
07546392
ABSTRACT:
A data transfer control apparatus includes a channel controller and plural transfer controllers. The channel controller receives, prioritizes and queues data transfer requests. An event to transfer controller table enables recall of a transfer controller number corresponding to the data transfer request. The plural transfer controllers are independent and can operate simultaneously in parallel. Each transfer controller includes a read bus interface and a write bus interface which arbitrate with other bus masters in the case of blocking accesses directed to interfering devices or address ranges.
REFERENCES:
patent: 6574683 (2003-06-01), Comisky et al.
patent: 6721822 (2004-04-01), Barry et al.
patent: 2001/0038634 (2001-11-01), Dally et al.
patent: 2003/0110325 (2003-06-01), Roach et al.
patent: 2006/0080478 (2006-04-01), Seigneret et al.
Castille Roger K.
Jones Jason A. T.
Lazar Marco
Nguyen Henry Duc C.
Seshan Natarajan Kurian
Brady III Wade J.
Marshall, Jr. Robert D.
Snyder Steven G
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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