Data transfer using two-stage bit switch in memory circuit

Details Data transfer using two-stage bit switch in memory circuit Data transfer using two-stage bit switch in memory circuit

2000-02-04

2001-01-09

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

For complementary information

C365S208000, C365S207000, C365S196000, C365S203000, C365S204000

Reexamination Certificate

active

06172920

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Technical Field
This invention relates to data transfer circuits in memory devices or the like, and more particularly to a two-stage bit switch for transferring data between bit lines in a memory device to data lines for output in a read operation.
2. Description of the Related Art
In a memory device of the type having an array of a large number of memory cells on a semiconductor chip, a read operation employs a pair of true and complement bit lines for a column of cells in the array, wherein the data on these bit lines is sensed and transferred to output circuitry. One of the ways to achieve high performance in these memory devices is to speed up this transfer of data in a read operation.
In some prior circuits used in transferring data from bit lines to output circuitry in a read operation, a direct connection between the bit lines and read data lines created a charge sharing problem, whereby data may possibly be read incorrectly. Thus, in order to avoid this charge sharing issue, it is preferred to couple the data on the bit lines to read data output circuitry by a path that does not permit direct currents to flow between the bit lines and the read data lines.
In prior arrangements for read data operations in memory circuits of this type, optimum speed is not achieved because of the time needed in a read operation to transfer data from the bit lines to the read data lines, a problem resulting in part from the delay needed to allow the bit lines to separate or develop a voltage differential large enough for unequivocal sensing in downstream circuitry in the read arrangement. Thus, it is preferable to enable sensing at an earlier point in the cycle of the read operation than has previously been allowed.
SUMMARY OF THE INVENTION
It is therefore one object of the present invention to provide an improved method of transferring data from bit lines in a read operation in a memory device.
It is another object of the present invention to provide an improved high speed data transfer circuit in a memory device, for moving data between bit lines of the memory array and data lines in a read-data output circuit.
It is yet another object of the present invention to provide improved performance in read data operations in memory devices by speeding up the generation of data in the read circuit at logic levels permitting sensing at earlier times in the cycle, while at the same time avoiding charge sharing issues.
The above as well as additional objects, features, and advantages of the present invention will become apparent in the following detailed written description.
According to one embodiment of the invention, a data transfer circuit for read data operations in a memory circuit employs a two-stage bit switch. True and complement bit lines from a memory cell array are coupled to gates of a pair of transistors in a first stage bit switch. The data from the bit lines is thus transferred to a pair of read data nodes without a DC connection, so charge-sharing is avoided. Also, this allows the data to be extracted without a full logic-level swing of the bit lines, so faster operation is provided. The data from the data nodes is transferred to a pair of data lines through a second-stage bit switch activated by a timing input. The differential voltage on the bit lines is enhanced by a sense amplifier, and, also, the use of the first-stage bit switch allows the bit lines to be precharged to only half the logic level, speeding up operation; this sense amplifier is activated before the timing input for the second-stage bit switch. The data lines are precharged then selectively discharged through source-to-drain paths of the transistors of the first and second stage bit switches


REFERENCES:
patent: 5742545 (1998-04-01), Kato
patent: 5983314 (1999-11-01), Merritt

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