Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1997-11-14
2001-07-24
Smith, Matthew S. (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C710S010000
Reexamination Certificate
active
06266797
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to computer chip architectures, and more particularly to an on-chip data transfer network which includes a multiple ring architecture with re-configurable paths for improved information routing between multiple on-chip modules.
2. Description of the Related Art
Computer systems have traditionally comprised a system unit or housing which comprises a plurality of electrical components comprising the computer system. A computer system typically includes a motherboard which is configured to hold the microprocessor and memory and the one or more busses used in the computer system. The motherboard typically comprises a plurality of computer chips or electrical components including intelligent peripheral devices, bus controllers, processors, bus bridges, etc.
More recently, computer systems are evolving toward an integration of functions into a handful of computer chips. This coincides with the ability of chip makers to place an increasingly large number of transistors on a single chip. For example, currently chip manufacturers are able to place up to ten million transistors on a single integrated circuit or monolithic substrate. It is anticipated that within several years chip makers will be able to place one billion transistors on a single chip. Thus, computer systems are involving toward comprising a handful of computer chips, where each computer chip comprises a plurality of functions. The integration of a plurality of modules or functions on a single computer chip requires an improved data transfer chip architecture. Also, due to the shorter distances and tighter integration of components on a chip, new data transfer architectures are necessary to take advantage of this environment. Therefore, an improved system and method is desired for including a plurality of different functions or modules on a single computer chip.
SUMMARY OF THE INVENTION
The present invention comprises a computer chip including a data transfer network. The data transfer network comprises a plurality of communication ports and a plurality of modules. Each of the communication ports is directly connected to two or more other communication ports, and each of the communication ports is operable to communicate data. The computer chip includes a plurality of buses connected between each of the communication ports. Each of the plurality of modules is coupled to at least one of the plurality of communication ports, and the plurality of modules are operable to communicate with each other through the communication ports. Furthermore, the plurality of communication ports are dynamically re-configurable to form two or more separate communication paths.
In one embodiment, the plurality of communication ports are bi-directionally coupled and are operable to communicate data with each other. The plurality of communication ports may also be dynamically re-configurable to form two or more communication rings. In another embodiment, a first plurality of communication ports comprise a first communication path, and a second plurality of communication ports comprise a second communication path. A first communication port in the first communication path is connected between two communication ports in the second communication path. The first communication port is then operable to transfer data between the two communication ports in the second communication path.
In another embodiment, the computer chip comprises a first plurality M of communication ports and a second plurality N of communication ports. The first plurality of communication ports are coupled and are operable to communicate data with each other. Likewise, the second plurality of communication ports are coupled and are operable to communicate data with each other. Each of the first plurality of communication ports is coupled to a corresponding one of the second plurality of communication ports. The first plurality of communication ports and the second plurality of communication ports arc also dynamically configurable to form two or more communication paths. The first plurality of communication ports may be bi-directionally coupled and operable to communicate data with each other, and the second plurality of communication ports may also be bi-directionally coupled and operable to communicate data with each other. The first plurality of communication ports and the second plurality of communication ports are preferably dynamically re-configurable to form one or more communication rings.
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Godfrey Gary M.
Hartmann Alfred C.
Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Siek Vuthe
Smith Matthew S.
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