Data transfer method/engine for pipelining shared memory bus acc

Details Data transfer method/engine for pipelining shared memory bus acc Data transfer method/engine for pipelining shared memory bus acc

1998-07-06

2000-12-26

Pan, Daniel H.

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

710 64, 710 61, 711169, 711147, G06F 1316, G06F 1336, G06F 1340, G06F 13366

Patent

active

061674753

ABSTRACT:
A data transfer engine, method and article of manufacture are provided for use in a functional unit of an integrated system for enhanced access and transfer of data over a shared data bus. The data transfer technique comprises pipelining data transfer requests onto the shared bus. The technique involves receiving and storing a first transfer parameter set in a primary parameter register within the data transfer structure, and receiving and storing a second transfer parameter set in a secondary parameter register within the transfer structure. Thereafter, data is transferred using the shared memory bus in response to the first transfer parameter set and the second transfer parameter set without relinquishing access to the shared memory bus between transferring of data in response to the different parameter sets. A situational wait decision is preferably implemented in practice to decide whether to pipeline consecutive data transfer requests based upon the characteristics of the first transfer parameter set and/or the second transfer parameter set, as well as the identities of the requesters providing the first transfer parameter set and the second transfer parameter set.

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"High-Speed Processor Bus Arbitration", IBM Technical Disclosure Bulletin, vol. 28, No. 12, May 1986, pp. 5329-5333.

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