Data transfer method

Details Data transfer method Data transfer method

2000-10-26

2004-03-23

Lee, Thomas (Department: 2185)

Electrical computers and digital processing systems: support

Clock control of data processing system, component, or data...

C713S400000

Reexamination Certificate

active

06711697

ABSTRACT:

FIELD OF THE INVENTION
The invention relates to a method of transferring serial data having a predetermined data length between a control device such as a CPU and a device such as a semiconductor IC to be controlled by the control device.
BACKGROUND OF THE INVENTION
A serial interface method is normally used in transferring predetermined data between a control device such as a CPU and a peripheral device such as an IC.
A typical serial interface method uses three data lines, including a data line SI for sending the serial data, a clock (CK) line, and a chip enablement (CE) line. Furthermore, if it is necessary, for example, to control 8-bit data as it is, an extra signal line for a data identification flag is needed to distinguish write data from command codes. Therefore, in total four lines are needed.
A serial data transfer method, called Inter Integrated Circuit (IIC) bus system, using only two data lines is also known in the art. In the IIC bus system, a master device and a multiplicity of IIC bus slave devices are connected via an IIC bus for exchange of address signals and data signals.
FIG. 1
shows a data format for use in an IIC bus system. As an example, in recording data in a predetermined IIC bus slave device via the IIC bus, the IIC bus master device raised a clock signal SCL to a HIGH level, while pulling data and address signals (SDA) from a HIGH to a LOW level. This establishes satisfactory conditions for data transfer, so that the bus master device sends an 8-bit address signal (A
7
-A
1
, R/W) to the IIC bus slave device. The eighth bit of the address signal (which corresponds to A
0
bit) is reserved for a read/write (R/W) bit which specifies a read or a write operation.
The IIC bus slave device addressed by the address signal returns an acknowledgment (ACK) signal to the IIC bus master device by lowering the SDA signal to the LOW level in the next clock subsequent to the eighth bit. Thus, the bus master device confirms that the IIC bus slave device is in the normal operating condition.
Upon receipt of the ACK signal, the IIC bus master device sends an 8-bit SDA data signal in synchronism with the clock signal SCL, which data signal is received and stored by the addressed IIC bus slave device. Upon receiving the data correctly, the addressed IIC bus slave device renders the SDA signal LOW, and returns an acknowledgment signal ACK. The IIC bus master device, upon receipt of the acknowledgment signal ACK, pulls up the SDA signals from the LOW to the HIGH level while the clock signal SCL is HIGH and ends the bussing operation.
Thus, in the IIC bus system, data transfer can be performed between a IIC bus master device and an arbitrary IIC bus slave device connected with the bus master device by means of two data transfer lines.
However, although such a conventional IIC bus system as mentioned above can transfer data using only two data lines, it require transfer of data amounting to a total of 18 bits in sending 8-bit data, including 7 bits slave device address and further bits for a R/W signal and an acknowledgment signal ACK, as shown in FIG.
1
. Moreover, in a case where a further signal must be included to indicate whether the serial data are data to be written in a device (referred to as write data) or a command code, additional 8 bits for the signal and a 1 acknowledgment bit, amounting to a total of 9 bits in a standard 8 bit data format, are needed for this purpose.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide a simple and efficient data transfer method in which serial data can be transferred, in a reduced data format, between a control device such as a CPU and a device such as a semiconductor IC to be controlled by the control device, using only two signal lines as in IIC data transfer systems.
Thus, in one aspect of the invention, there is provided a serial data transfer method utilizing one clock line and one serial data line, comprising steps of:
transferring a predetermined number of serial data bits on said serial data line, with each bit in synchronism with a rise or a fall of a clock signal on said clock line;
placing a chip enablement signal in synchronism with a particular fall or rise of the clock signal associated with a particular one of said data bits; and
determining the range of said serial data based on said chip enablement signal.
It is noted that in transferring serial data from a control device such as a CPU to a slave device such as ICs, the chip enablement signal is placed at a predetermined bit position within the serial data bits, thereby reducing the data length to that of the serial data passed by two signal lines as in conventional IIC data transfer, thereby allowing simple yet efficient data transfer.
A data identification flag to distinguish serial data constituting a command code from serial data constituting write data may also be placed in the data bit that follows the chip enablement signal bit in synchronism with the falling or rising clock signal associated with the data bit.
The chip enablement signal allows determination of the data range of the sequential data. The data identification flag allows to distinguish write data from command codes.
In the data transfer system according to the invention, the above mentioned particular data bit to which said chip enablement signal is associated may be the second bit from the last in the serial data. This assures detection of the chip enablement signal.
The serial data bits may be sequentially read in and stored in registers by shifting the data bits in synchronism with the rising or fall clock signal. The serial data may be retrieved after the predetermined range of data bits are shifted in the registers following the detection of the chip enablement signal.
It should be appreciated that signals received are sequentially shifted in the registers and stored therein without querying whether the signals are valid sequential data or not, and that the serial data are retrieved when its validity is verified, thereby assuring receipt of the serial data by the addressed slave device in a simple and safe manner.
In cases where one-way data transfer is required, serial data transfer method of the invention is particularly useful.


REFERENCES:
patent: 4890222 (1989-12-01), Kirk
patent: 5406403 (1995-04-01), Griffin et al.
patent: 5530676 (1996-06-01), Sullivan et al.
patent: 5535333 (1996-07-01), Allen et al.
patent: 5826068 (1998-10-01), Gates
patent: 6081656 (2000-06-01), Witt
patent: 275411 (1988-07-01), None
patent: 883066 (1998-12-01), None
Xilinx, IIC Bus Interface Design Specification, Dec. 20, 2001.

Affiliated with

Also associated with

Rating

Data transfer method does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Data transfer method, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Data transfer method will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3221745