Electrical computers and digital processing systems: memory – Storage accessing and control – Access timing
Reexamination Certificate
1998-08-05
2002-05-21
Yoo, Do Hyun (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Access timing
C711S005000, C713S500000, C365S230030, C365S233100
Reexamination Certificate
active
06393541
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer memory comprising a plurality of memory devices such as a plurality of dynamic random access memories (DRAMs) having the function of transferring data on one system bus within a bus system, or a plurality of memory modules each having such memory devices mounted therein.
Generally, for improving an efficiency of a whole bus system, various kinds of data items must be input or output at high speed between a plurality of memory devices or memory modules and a central processing unit (CPU).
The present invention relates to a data transfer memory device constructed by arranging a plurality of memory devices on a system bus or arranging a plurality of memory modules, each of which has the plurality of memory devices mounted therein, on the system bus. The present invention refers to a technique for continuously transferring various kinds of data items, which are an object of input or output from or to each memory device or memory module, at high speed over a bus line included in the system bus.
2. Description of the Related Art
For an easy understanding of problems underlying a data transfer memory of a prior art, a bus system employing the data transfer memory of the prior art will be described with reference to
FIGS. 1
to
3
that will be described in “BRIEF DESCRIPTION OF THE DRAWINGS”.
FIG. 1
shows a configuration of a bus system according to the first example of the prior art. The bus system comprises a plurality of memory devices realized with a plurality of Rambus DRAMs that operate in a Rambus mode, or a plurality of memory modules each having the plurality of Rambus DRAMs mounted therein. Note that data transfer bus lines (normally referred to as DQ lines) included in a system bus
7
are omitted from the drawing.
Furthermore, referring to
FIG. 1
, one chip set (chip set #0)
40
realized with a CPU or the like, a reference signal generator
42
, first to m-th memory devices or memory modules
100
-
1
,
100
-
2
, etc., and
100
-
m
(hereinafter a plurality of memory devices or memory modules
100
-
1
to
100
-
m
where m denotes any positive integer) are interconnected on a clock line included in the system bus
7
. The clock line is turned back and used as a data output clock line for use in sending a clock from the plurality of memory devices or memory modules
100
-
1
to
100
-
m
to the chip set
40
, and a data input clock line for use in sending a clock from the chip set
40
to the plurality of memory devices or memory modules
100
-
1
to
100
-
m.
Herein, a transfer clock T-CLK is transferred over the data output clock line, and a receive clock R-CLK is transferred over the data input clock line. In this case, the transfer clock T-CLK and receive clock R-CLK are transferred using the same clock line alone. It is thus prevented that data input to each memory-device or memory module and data output from each memory device or memory module become out of phase with each other. The level of a signal on the clock line is adjusted using a voltage supplied from a power supply Vt via a level adjustment resistor Rt
1
.
In the bus system of the first example of the prior art shown in
FIG. 1
, whichever of the plurality of memory devices that are Rambus DRAMs is accessed, data items output from the plurality of memory devices or memory modules to the chip set
40
have the same timing. However, when a signal delay time t dependent on a system bus length L or the length of bus lines constituting the system bus becomes equal or longer than a half of a data transfer time, the time from the moment when a protocol is input synchronously with the receive clock R-CLK until data is output synchronously with the transfer clock T-CLK becomes short. The upper limit of the system bus length L is therefore restricted. As a data transfer rate increases and becomes higher, the system bus length L must be made smaller.
On the other hand, the time necessary for an acknowledge packet to arrive at the chip set may be monitored. This enables the chip set to detect arrival of data in advance. However, the time necessary for the acknowledge packet to arrive at the chip set is determined by a distance from each memory device or memory module. The chip set must therefore wait for the time.
FIG. 2
shows a configuration of a bus system in accordance with the second example of the prior art. The bus system comprises a plurality of memory devices that operate in a DQ strobe mode, or a plurality of memory modules each having the memory devices mounted therein. Note that a DQ line included in a system bus
7
is omitted from the drawing.
Furthermore, referring to
FIG. 2
, bus lines constituting the system bus
7
include an MCLK line for use in transferring a main clock MCLK to be sent from one chip set
40
such as a CPU to first to m-th memory devices or memory modules
110
-
1
,
110
-
2
, etc., and
110
-
m
(hereinafter a plurality of memory devices or memory modules
110
-
1
to
110
-
m
), and a DQS line for use in transferring a DQ strobe DQS originated when data is output from any of the plurality of memory devices or memory modules
110
-
1
to
110
-
m
. The level of a signal on the MCLK line is adjusted using a voltage supplied from a power supply Vt via a level adjustment resistor Rt
2
. The level of a signal on the DQS line is adjusted using a voltage supplied from the power supply Vt via another level adjustment resistor Rt
3
.
Furthermore, referring to
FIG. 2
, the chip set
40
, reference signal generator
42
, and plurality of memory. devices or memory modules
110
-
1
to
110
-
m
are interconnected on the MCLK line and DQS line.
In the bus system of the second example of the prior art shown in
FIG. 2
, the plurality of memory devices or memory modules
110
-
1
to
110
-
m
receive input data synchronously with the main clock MCLK. On the other hand, the plurality of memory devices or memory modules each output data synchronously with the DQ strobe DQS generated by the memory device or memory module during data output (that is, data reading).
Furthermore, according to another method, when data is input to the plurality of memory devices or memory modules (that is, during data writing), the chip set
40
controls a DQ strobe terminal. The plurality of memory devices or memory modules receives input data according to the timing of controlling the DQ strobe terminal.
According to this method, a signal delay time t dependent on a system bus length L arises. The time necessary for a memory device or memory module to receive a read instruction for instructing data reading, or the time necessary for the chip set
40
to receive data output from a memory device or memory module varies depending on the position of the memory device or memory module. In this case, a first access time necessary for the chip set
40
to receive data for the first time after the chip set
40
issues the read instruction cannot be controlled by the chip set
40
. The chip set
40
must therefore change the position of a data reception window according to data output from a memory device or memory module.
In particular, the time required to receive data output from the first memory device or memory module
110
-
1
located closest to the chip set
40
differs greatly from the time required to receive data output from the m-th memory device or memory module
110
-
m
located farthest from the chip set
40
. Every time the chip set
40
receives data from any of the memory devices or memory modules, it must reset the position of the data reception window.
FIG. 3
shows a configuration of a bus system in accordance with the third example of the prior art. The bus system comprises a plurality of memory modules each having a plurality of memory devices, which operate in a return clock mode, mounted therein.
Furthermore, referring to
FIG. 3
, bus lines constituting a system bus
7
include an MCLK line for use in transferring a main clock MCLK, which is sent from a chip set
40
to first to m-th memor
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fujitsu Limited
Namazi Mehdi
Yoo Do Hyun
LandOfFree
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