Data transfer memory

Details Data transfer memory Data transfer memory

2007-01-23

2007-01-23

Auve, Glenn A. (Department: 2111)

Electrical computers and digital data processing systems: input/

Intrasystem connection

Bus access regulation

C713S400000, C710S305000

Reexamination Certificate

active

11068601

ABSTRACT:
A data transfer memory for reducing the number of components in an electronic module. A master controller circuit provides a transfer start command to a master clock signal generator circuit when receiving an activation detection signal from a power activation detection circuit. As a result, the master clock signal generator circuit generates a basic clock signal, outputs the basic clock signal to an SCL line, and has a master transfer sequencer circuit execute a transfer sequence. The master transfer sequencer circuit transmits a start condition, data stored in the nonvolatile memory via a serial control circuit, and a stop condition to an SDA line synchronously with the basic clock signal.

REFERENCES:
patent: 2004/0139258 (2004-07-01), Chambers
patent: 2005/0005049 (2005-01-01), Montalvo et al.

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