Data transfer in a memory device having complete row redundancy

Details Data transfer in a memory device having complete row redundancy Data transfer in a memory device having complete row redundancy

1998-07-01

1999-09-14

Nelms, David

Static information storage and retrieval

Read/write circuit

365149, 365154, 365200, 36523005, G11C 700

Patent

active

059532580

ABSTRACT:
An ATM switch including a multi-port memory is described. The multi-port memory has a dynamic random access memory (DRAM) and input and output serial access memories (SAMs). The multi-port memory includes an array of primary and redundant memory cells. Data transfer buses are described which traverse the array and can be coupled to either the primary or redundant memory cells. Redundant row enable circuitry is described which enables an entire row of redundant memory cells to be substituted for any row of primary memory cells.

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