Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
2001-11-30
2003-06-03
Ray, Gopal C. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
C710S052000, C710S071000, C710S313000, C375S222000
Reexamination Certificate
active
06574697
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to data transfer equipment to transfer data between data terminal equipment (hereinafter referred to as a “DTE”) such as a personal computer and data circuit terminating equipment (hereinafter referred to as a “DCE”) being connected to the DTE such as a communication MODEM (Modulator-demodulator).
2. Description of the Related Art
Conventionally, for example, when data communications are carried out between a personal computer and a peripheral unit such as the communication MODEM, the personal computer is used as the DTE and the communication MODEM is used as the DCE. Inside the DTE and the DCE, a parallel bus to speed up data processing is provided and, for example, a PCI (Peripheral Component Interconnect) bus extending from the microprocessor is installed in the DTE. When the DTE is connected to the DCE at specified intervals, because data synchronous processing required for parallel bus connection is not necessary which can provide an advantage to data transmission carried out over a comparatively long distance, generally, serial bus connection is employed. Thus, the DTE and the DCE are connected using a specified serial bus cable. To the PCI placed in the DTE is connected to data transfer equipment having an UART (Universal Asynchronous Receiver/Transmitter) which can perform a function of a parallel to serial transfer. The UART can be applied to many receiving and transmitting circuits to carry out start-stop synchronous type communications being so-called asynchronous type communications and the UART is integrated on one chip as a controller which performs start-up synchronous system type serial data transmission for general purposes. The UART is provided with functions of serial data communication including detection and removal of start-stop bits, selection and control of the number of data bits or stop bits, generation and detection of a break sequence, detection of overrun or framing errors or a like. RS-232C standards designated by EIA (Electronic Industries Association) which are widely known as interface standards for control measuring instruments, communication devices or a like can be applied to the above UART. Therefore, many pieces of software corresponding to controlling procedures for the UART in accordance with the RS-232C are installed on many pieces of DTE. The above DCE is connected to a serial bus such as the RS-232C based serial bus extending from the data transfer equipment placed in the DTE. The DCE is provided with a data transfer equipment, same as the data transfer equipment mentioned above, that can perform a serial/parallel converting function corresponding to the serial bus, which enables the DCE to convert data received through the serial bus to data corresponding to its parallel bus. When the data communications are carried out between the DTE and the DCE, the data transfer equipment in the DTE converts data fed through the PCI bus of the DTE into serial data by the start-stop synchronous method and transfers the serial data through the serial bus to the data transfer equipment in the DCE. Besides, the data transfer equipment in the DTE converts the serial data fed, by the start-stop synchronous method, through the serial bus from the data transfer equipment in the DCE into data that can be matched to a size of the PCI bus on the side of the DTE and transfers the parallel data to the DTE.
As the DCE to be connected to the DTE, a so-called PHS (Personal Handyphone System) card serving as a card-type wireless communications device is used in some cases. Such the card-type DCE is inserted, for use, in a specified slot directly connected to the PCI bus in the DTE. Generally, the PHS card is provided with one data transfer equipment connected to the PCI bus on the DTE side and with the other data transfer equipment connected through the serial bus to the one data transfer equipment. The data fed from the serial bus, after having undergone the serial/parallel converting processing by the other data transfer equipment, is transmitted through the parallel bus extending from the other data transfer equipment to a wireless communications section.
However, when the RS-232C standards, for example, are applied to the serial bus provided in the card-type wireless communications equipment as described above, a maximum speed of a baud rate generator implemented on a UART chip of the data transfer equipment is about 115 kbps. Such a low speed serial transfer capability causes a bottleneck that imposes a limitation on the transfer speed between the DTE and the DOE.
SUMMARY OF THE INVENTION
In view of the above, it is an object of the present invention to provide data transfer equipment capable of implementing high-speed data transmission comparatively easily in data transfer between the DTE and DCE.
According to a first aspect of the present invention, there is provided data transfer equipment for serving the DCE which is connected through a first parallel bus provided in the DTE and has a data processing section used to process data to be exchanged with the DTE, including:
a transfer processing section connected through a second parallel bus to the data processing section to transfer, based on specified control procedures except procedures for a parallel/serial data converting function out of control procedures for a UART, data received through the first parallel bus from the DTE to the data processing section through the second parallel bus and to transfer, based on the specified control procedures, data received through the second parallel bus from the data processing section to the DTE.
In the foregoing, a preferable mode is one wherein the transfer processing section is provided with a first storing section used to store, on a temporary basis, data received through the first parallel bus from the DTE, a second storing section used to store, on a temporary basis, data received through the second parallel data from the data processing section and a first register used to store, on a temporary basis, data stored in the first storing section and the second storing section which is used when the DTE and the DCE write or read data to or from each of the first and second storing sections.
Also, a preferable mode is one wherein the transfer processing section is further provided with a control section used to feed control signals to permit each of the DTE and DCE to read data from each of the first and second storing sections and to permit each of the DTE and DCE to write data to each of the first and second storing sections, a second register used to hold each of the control signals to be fed to the DTE and a third register used to hold each of the control signals to be fed to the data processing section.
Also, a preferable mode is one that wherein includes:
a plurality of transfer processing sections including the transfer processing section; and
an identifying section used to identify each of the transfer processing sections.
Also, a preferable mode is one wherein the DCE is a card-type communication MODEM device which is inserted for use into a predetermined slot of the DTE.
Also, a preferable mode is one wherein the data processing section in the DCE has a wireless communicating function.
Also, a preferable mode is one wherein the first parallel bus is a PCI bus.
Also, a preferable mode is one wherein the writing and reading of data to and from each of the first and second storing sections are performed in a FIFO (First In First Out) method.
With the above configuration, the high-speed data transfer between the DTE and the DCE can be implemented comparatively easily without the need for a high-speed clock that has been required in the conventional transfer equipment.
REFERENCES:
patent: 4377843 (1983-03-01), Garringer et al.
patent: 5115374 (1992-05-01), Hongoh
patent: 5309504 (1994-05-01), Morganstein
patent: 5550566 (1996-08-01), Hodgson et al.
patent: 5907719 (1999-05-01), Nimishakavi
patent: 6167120 (2000-12-01), Kikinis
Fujii Mineo
Shinagawa Noriaki
Oki Electric Industry Co. Ltd.
Ray Gopal C.
Volentine & Francos, PLLC
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