Data transfer device with a post charge logic

Details Data transfer device with a post charge logic Data transfer device with a post charge logic

1999-06-29

2001-04-03

Tokar, Michael (Department: 2819)

Electronic digital logic circuitry

Interface

Current driving

C326S093000, C326S112000

Reexamination Certificate

active

06211700

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a data transfer device with a post charge logic. In particular, it relates to a data transfer device with a post charge logic, which initializes data lines in a memory device after data is transferred.
2. Description of the Prior Art
In general, a post charge operation is to initialize data lines by using the signals transferred on the data lines, after a data receiving circuit has received data outputted from a data transferring circuit through the data lines.
FIG. 1
represents a circuit diagram of a conventional data transfer device with a post charge logic circuit. In the diagram, each of the data bus sense amplifiers
10
and
40
is coupled to the corresponding receiving parts
20
and
50
through corresponding data line pairs DL
1
, DL
2
and DL
3
, DL
4
.
The data bus sense amplifiers
10
and
40
transfer high/low level data to the receiving part
20
and
50
through the corresponding data line pairs DL
1
, DL
2
and DL
3
, DL
4
. This is conducted by controlling the data driving elements N
1
, N
2
, N
3
, and N
4
provided between the data lines DL
1
, DL
2
, DL
3
, and DL
4
and ground voltage.
As shown in
FIG. 1
, post charge logic circuits
30
and
32
are provided on the data line pair DL
1
and DL
2
to initialize the data lines after the data has been transferred from the data bus sense amplifier
10
to the data lines. Post charge logic circuits
60
and
62
are provided on the data line pair DL
3
and DL
4
to initialize the data lines after the data has been transferred from the data bus sense amplifier
40
to the data lines.
The post charge logic circuit
30
comprises an inverter circuit
30
a
for receiving data on the data line DL
1
, delay circuit
30
b
for delaying the output signal from the inverter
30
a
for a predetermined time, an inverter circuit
30
c
for receiving the output signal from the delay circuit
30
b,
and a switching element P
1
(wherein P
1
is a PMOS transistor) for controlling the voltage level on the data line DL
1
in response to an output signal from the inverter
30
c.
The construction of the other post charge logic circuits
32
,
60
, and
62
is identical with that of the post charge logic circuit
30
.
The operation of the conventional data trnsfer device with a post charge logic in consideration of the operations of the data bus sense amplifier and the receiving part will be expalined hereinafter in detail.
The operation which transfers high level data to the receiving parts will be illustrated. At the beginning, the voltage levels of the data lines DL_
1
, and DL_
2
are predetermined by a pheriperal circuit (not shown), and generally are set to a high level. When one (for example, N
1
) of the data driving elements N
1
and N
2
is turned on in response to the output signal from the data bus sense amplifier
10
, the voltage level of the data line DL
1
is changed from a high level to a low level.
In the beginning, the PMOS transistor P
1
within the post charge logic circuit
30
is turned off until the data line DL
1
has changed from a high level to a low level, thus the voltage of the data line DL
1
is high level. When the voltage level of the data line DL
1
has changed to a low level, the PMOS P
1
will be turned on after a time lapse.
Therefore, the voltage level of the data line DL
1
is initialized in response to the turned on PMOS transistor P
1
after the signal of high data has been transferred to the receiving part.
On the contrary, the operation which transfers high level data to the receiving parts will be illustrated. At the beginning, the voltage levels of the data lines DL_
1
, and DL_
2
are predetermined by a pheriperal circuit (not shown), and generally are set to a high level. When one (for example, N
2
) of the data driving elements N
1
and N
2
is turned on in response to the output signal from the data bus sense amplifier
10
, the voltage level of the data line DL
2
is changed from a high level to a low level. The PMOS transistor P
2
within the post charge logic circuit
32
is turned off until the data line DL
2
has changed from a high level to a low level, thus the voltage of the data line DL
2
is high level.
When the voltage level of the data line DL
2
has changed to a low level, the PMOS P
2
will be turned on after a time lapse.
Therefore, the voltage level of the data line DL
2
is initialized in response to the turned on PMOS transistor P
2
after the signal of high data has been transferred to the receiving part.
The operation of the other data bus sense amplifier
40
and receving part
50
is identicel with that of the data transfer device illustrated above. In general, there is a plurality of data bus sense amplifiers and receving parts in the data transfer device.
As shown in FIG.
1
and illustrated above, the conventional data transfer device comprises a plurality of post charge logic circuits, each of which is provided on the each data line, resulting in an increase in the power consumption and an increase in a layout area.
SUMMARY OF THE INVENTION
Accordingly, the present invention for resolving the above illustrated problems is directed to a data transfer device with a post charge logic circuit which performs a post charge operation to a plurality of data line pairs by using of the signals only one data line pair.
To achieve the above object, a data transfer device according to the present invention includes: a plurality of data transferring means; a plurality of data line pairs; a plurality of driving means connected between each of the data lines and ground voltage; a plurality of data receiving means connected to a plurality of driving means through a plurality of data line pairs; and a post charge logic means for receiving a pair of data onto a pair of data line pair of the plurality of data line pairs and for performing a post charge operation at all of the plurality of data line pairs.


REFERENCES:
patent: 5479646 (1995-12-01), Proebsting
patent: 5532622 (1996-07-01), Beiley et al.
patent: 5543735 (1996-08-01), Lo
patent: 5767700 (1998-06-01), Lee
patent: 6087855 (2000-07-01), Frederick, Jr. et al.

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