Data transfer device for transferring data between blocks of...

Electronic digital logic circuitry – Interface – Current driving

Reexamination Certificate

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C327S297000, C341S100000

Reexamination Certificate

active

06911843

ABSTRACT:
The number of pulses of a clock signal CLK-A is circularly counted in a count range from “0” to “7”, and count signals indicating count values are produced. A clock signal CLK-B having a frequency lower than that of the clock signal CLK-A is produced from count signals of “3” and “7”, and data transfer between a high speed operating block operated in synchronization with the clock signal CLK-A and a low speed operating block operated in synchronization with the clock signal CLK-B is performed in synchronization with the clock signal CLK-B to receive input serial data or transmit output serial data. When a stuff bit of universal Serial Bus is detected in the input serial data or is inserted in the output serial data, a cycle of the clock signal CLK-B is lengthened by one cycle of the clock signal CLK-A.

REFERENCES:
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patent: 5293628 (1994-03-01), Langan et al.
patent: 5598446 (1997-01-01), Van Der Tuijn
patent: 6097674 (2000-08-01), Swapp
patent: 6259283 (2001-07-01), Nguyen
patent: 1172960 (2002-01-01), None
patent: 2001-268142 (2001-09-01), None
“Universal Serial Bus Specification,” Revision 2.0, http://www.usb.org/developers/data/usb_20.zip Apr 27, 2000, pp. 157-158.
USB 2.0 Transceiver Macrocell Interface (UTMI) Specification 1999-2001 Intel Corporation, Ver. 1.05, http://developer.intel.com/technology/usb/download/2_0_Xcvr_Macrocell_1_05.pdf Mar. 29, 2001, P23 5.6 Bit Unstuff Logic & Figure 5.
USB 2.0 Transceiver Macrocell Interface (UTMI) Specification 1999-2001 Intel Corporation, Ver. 1.05, http://developer.intel.com/technology/usb/download/ 2_0_Xcvr_Macrocell_1_05.pdf Mar. 29, 2001, P29 5.11 Bitstuff Logic & Figure 11.

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