Data transfer device and multiprocessor system

Details Data transfer device and multiprocessor system Data transfer device and multiprocessor system

1994-03-03

1996-04-30

Harvey, Jack B.

395405, G06F 1300

Patent

active

055133649

ABSTRACT:
In a data transfer control device for controlling a data transfer bus connected to plural buffer units, an address generation circuit for specifying a buffer unit address is provided with an address register for holding upper and lower limit values of the buffer unit address, an address counter which sequentially increments the buffer unit address, starting from the lower limit value, and a comparator for judging whether an output of the address counter reaches to the upper limit value. The data transfer control device composes a crossbar-type data transfer network together with the buffer units, and plural processor elements or plural I/O devices are connected to the network.

REFERENCES:
patent: 4514807 (1985-04-01), Nogi
patent: 4855903 (1989-08-01), Carleton et al.
patent: 5134695 (1992-07-01), Ikeda

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