Electrical computers and digital data processing systems: input/ – Input/output data processing – Peripheral configuration
Reexamination Certificate
1994-03-08
2001-02-06
Vu, Viet D. (Department: 2758)
Electrical computers and digital data processing systems: input/
Input/output data processing
Peripheral configuration
C710S013000, C710S120000, C711S001000, C711S005000, C711S170000
Reexamination Certificate
active
06185629
ABSTRACT:
NOTICE
© Copyright, {circle around (m)} Texas Instruments Incorporated 1991. A portion of the disclosure of this patent document contains material which is subject to copyright and mask work protection. The copyright and mask work owner has no objection to the facsimile reproduction by anyone of the patent document or the patent disclosure, as it appears in the Patent and Trademark Office patent file or records, but otherwise reserves all copyright and mask work rights whatsoever.
TECHNICAL FIELD OF THE INVENTION
The technical field of this invention is the field of digital data processing and more particularly microprocessor circuits, architectures and methods for digital data processing especially digital image/graphics processing.
BACKGROUND OF THE INVENTION
The inventive embodiments have many applications some of which relate to the field of computer graphics, discussed herein as an illustrative background. In a field of computer graphics known as bit mapped graphics, computer memory stores data for each individual picture element or pixel of an image at memory locations that correspond to the location of that pixel within the image. This image may be an image to be displayed or a captured image to be manipulated, stored, displayed or retransmitted. The field of bit mapped computer graphics has benefited greatly from the lowered cost and increased capacity of dynamic random access memory (DRAM) and the lowered cost and increased processing power of microprocessors. These advantageous changes in the cost and performance of component parts enable larger and more complex computer image systems to be economically feasible.
The field of bit mapped graphics has undergone several stages in evolution of the types of processing used for image data manipulation. Initially a computer system supporting bit mapped graphics employed the system processor for all bit mapped operations. This type of system suffered several drawbacks. First, the computer system processor was not particularly designed for handling bit mapped graphics. Design choices that are very reasonable for general purpose computing are unsuitable for bit mapped graphics systems. Consequently some routine graphics tasks operated slowly. In addition, it was quickly discovered that the processing needed for image manipulation of bit mapped graphics was so loading the computational capacity of the system processor that other operations were also slowed.
The next step in the evolution of bit mapped graphics processing was dedicated hardware graphics controllers. These devices can draw simple figures, such as lines, ellipses and circles, under the control of the system processor. Some of these devices can also do pixel block transfers (PixBlt). A pixel block transfer is a memory move operation of image data from one portion of memory to another. A pixel block transfer is useful for rendering standard image elements, such as alphanumeric characters in a particular type font, within a display by transfer from nondisplayed memory to bit mapped display memory. This function can also be used for tiling by transferring the same small image to the whole of bit mapped display memory. Built-in algorithms for performing some of the most frequently used graphics functions provide a way of improving system performance. Also a graphics computer system may desirably include other functions besides those few that are implemented in such a hardware graphics controller. These additional functions might be implemented in software by the system processor. These hardware graphics controllers will typically allow the system processor only limited access to the bit map memory. This limits the degree to which system software can augment the fixed set of functions of the hardware graphics controller.
The graphics system processor represents yet a further step in the evolution of bit mapped graphics processing. A graphics system processor is a programmable device that has all the attributes of a microprocessor and also includes special functions for bit mapped graphics. The TMS34010 and TMS34020 graphics system processors manufactured by Texas Instruments Incorporated represent this class of devices. These graphics system processors respond to a stored program in the same manner as a microprocessor and include the capability of data manipulation via an arithmetic logic unit, data storage in register files and control of both program flow and external data memory. In addition, these devices include special purpose graphics manipulation hardware that operate under program control. Additional instructions within the instruction set of these graphics system processors control the special purpose graphics hardware. These instructions and the hardware that supports them are selected to perform base level graphics functions that are useful in many contexts. Thus a graphics system processor can be programmed for many differing graphics applications using algorithms selected for the particular problem. This provides an increase in usefulness similar to that provided by changing from hardware controllers to programmed microprocessors. Because such graphics system processors are programmable devices in the same manner as microprocessors, they can operate as stand alone graphics processors, graphics co-processors slaved to a system processor or tightly coupled graphics controllers.
Several fields would desirably utilize more cost effective, powerful graphics operations to be economically feasible. These include video conferencing, multi-media computing with full motion video, high definition television, color facsimile, smart photocopiers, image recognition systems and digital photography, among other examples. Each of these fields presents unique problems. Image data compression and decompression are common themes in some of these applications. The amount of transmission bandwidth and the amount of storage capacity required for images and particular full motion video is enormous. Without efficient video compression and decompression that result in acceptable final image quality, these applications will be limited by the costs associated with transmission bandwidth and storage capacity. There is also a need in the art for a single system that can support both image processing functions such as image recognition and graphics functions such as display control.
SUMMARY OF THE INVENTION
This invention is a data processing apparatus which may interface with plural types of memories. A static decoder coupled to an external port decodes signals which from an external source that indicate the type of memory. Interface circuitry receives coded information from the static decoder and selects a protocol for information transfer. In the preferred embodiment, the protocol includes addressing information having multiplexed row/column addresses for accessing dynamic memories or un-multiplexed addresses for accessing static memories.
The interface circuitry further includes a column address shifter. The column address shifter shifts address bits to vary the number of bits available for column addressing. The permits memory accesses to memories of differing sizes which require differing numbers of address bits.
The data processing apparatus attempts to use page mode addressing whenever possible. A lastpage register coupled to the address generator for stores previous address information. A comparator compares the previous address information stored in the lastpage register to the current address. This permits detection of the occurrence of a page change. If no page change is detected, the data processor supplies only the column address to the memory in a page mode cycle. If a page change is detected, the data processor supplies a full new address including both the row address and the column address. A static decoder coupled to an external port receives externally generated page size signals. A page size decoder decodes the page size signals. This permits control of the number of bits of the lastpage register employed in the comparison. Thus the page change detection can be mad
Balmer Keith
Robertson Iain
Simpson Richard
Brady III W. James
Marshall, Jr. Robert D.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
Vu Viet D.
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