Data transfer controller and electronic device

Details Data transfer controller and electronic device Data transfer controller and electronic device

2005-02-08

2005-02-08

Fleming, Fritz M. (Department: 2182)

Electrical computers and digital data processing systems: input/

Input/output data processing

C710S005000, C710S033000

Reexamination Certificate

active

06854020

ABSTRACT:
The objective is to provide a data transfer control device and electronic equipment that are capable of reducing processing overheads, thus enabling high-speed data transfer within a compact hardware configuration. During IEEE 1394 data transfer, a packet assembly circuit (280) reads a header and data for a packet from header and data areas in a RAM (80) and links them together. The period of time during which a header CRC is created is used to obtain a data pointer. Whether a header or data is being read is determined by tcode, and the header pointer or data pointer incremented accordingly. A header is created while data is being fetched from the data area. Data is fetched to one channel which a packet is being transmitted from another channel within a divided send packet area. A linkage pointer is used to sequentially read a packet from another channel. An ACK code from the transfer destination is written back to the channel that sent the corresponding packet. Packets can be sent in series by rewriting a basic header to sequentially create headers until a number-of-repeats reaches zero.

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“Real-Time Transfer Modes and Multimedia-Capable Protocols for IEEE 1394-1995 (FireWire)” (Interface, Jan. 1997, pp. 136-146).

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